XR16C2850IJ EXAR [Exar Corporation], XR16C2850IJ Datasheet - Page 11

• Manufacturer Part Number: XR16C2850IJ
• Description: 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
• Manufacturer: EXAR [Exar Corporation]

xr
REV. 2.1.3
Typical oscillator connections are shown in
application note DAN108 on EXAR’s web site.
A single Baud Rate Generator (BRG) is provided for the transmitter and receiver, allowing independent TX/RX
channel control. The programmable Baud Rate Generator is capable of operating with a crystal frequency of
up to 24 MHz. However, with an external clock input on XTAL1 pin and a 2K ohms pull-up resistor on XTAL2
pin (as shown in
sampling) at room temperature and 5.0V.
F
Each UART also has their own prescaler along with the BRG. The prescaler is controlled by CLKSEL hardware
pin or a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input crystal or
external clock by 1 or 4 and can override the CLKSEL pin following reset. The clock output of the prescaler
goes to the BRG. The BRG further divides this clock by a programmable divisor between 1 and (2
obtain a 16X sampling rate clock of the serial data rate. The sampling rate clock is used by the transmitter for
data bit shifting and receiver for data sampling.
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate.
clock at 16X sampling rate clock rate. A 16X sampling clock is typically used. However, user can select the 8X
sampling clock rate mode to double the operating data rate. When using a non-standard data rate crystal or
external clock, the divisor value can be calculated for DLL/DLM with the following equation.
2.9
IGURE
5. E
Programmable Baud Rate Generator
XTERNAL
F
IGURE
XTAL1
XTAL2
Figure
Table 5
6. B
C
LOCK
5) it can extend its operation up to 50 MHz (3.125 Mbps serial data rate and 16X
AUD
C
shows the standard data rates available with a 14.7456 MHz crystal or external
R
ONNECTION FOR
Crystal
Buffer
Osc/
ATE
G
ENERATOR AND
vcc
gnd
External Clock
Divide by 4
Divide by 1
Prescaler
Figure
Prescaler
E
XTENDED
R1
2K
VCC
P
11
4. For further reading on oscillator circuit please see
RESCALER
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
D
MCR Bit-7=0
MCR Bit-7=1
XTAL1
XTAL2
ATA
(default)
R
ATE
Baud Rate
DLL and DLM
Generator
Registers
Logic
Rate Clock to
Transmitter
Sampling
16X
XR16C2850
16
-1) to