XR16M781IL24 EXAR [Exar Corporation], XR16M781IL24 Datasheet - Page 32
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XR16M781IL24
Manufacturer Part Number
XR16M781IL24
Description
1.62V TO 3.63V UART WITH 64-BYTE FIFO AND VLIO INTERFACE
Manufacturer
EXAR [Exar Corporation]
Datasheet
1.XR16M781IL24.pdf
(52 pages)
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XR16M781
1.62V TO 3.63V UART WITH 64-BYTE FIFO AND VLIO INTERFACE
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
•
•
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM/DLD) enable.
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•
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
•
•
MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.
•
•
MCR[2]: Reserved
OP1# is not available as an output pin on the M781. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
MCR[3]: INT Output Enable
Enable or disable INT outputs to become active or in three-state. This bit is also used to control the OP2#
signal during internal loopback mode.
•
•
4.7
Logic 0 = No TX break condition. (default)
Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
Logic 0 = Data registers are selected. (default)
Logic 1 = Divisor latch registers are selected.
Logic 0 = Force DTR# output HIGH (default).
Logic 1 = Force DTR# output LOW.
Logic 0 = Force RTS# output HIGH (default).
Logic 1 = Force RTS# output LOW. It is required to start Auto RTS Flow Control.
Logic 0 = INT output disabled (three state). During internal loopback mode, OP2# is HIGH.
Logic 1 = INT output enabled (active). During internal loopback mode, OP2# is LOW.
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
MCR
B
IT
0
1
-3
T
ABLE
11: INT O
INT O
Three-State
32
Active
UTPUT
UTPUT
M
ODES
REV. 1.0.1