71M6543GH MAXIM [Maxim Integrated Products], 71M6543GH Datasheet - Page 110

• Manufacturer Part Number: 71M6543GH
• Description: Selectable Gain of 1 or 8 for One Current Energy Meter ICs Metrology Compensation
• Manufacturer: MAXIM [Maxim Integrated Products]

71M6543F/H and 71M6543G/GH Data Sheet
110
Name
LCD_DAC[4:0]
LCD_E
LCD_MAP[55:48]
LCD_MAP[47:40]
LCD_MAP[39:32]
LCD_MAP[31:24]
LCD_MAP[23:16]
LCD_MAP[15:8]
LCD_MAP[7:0]
LCD_MODE[2:0]
LCD_ON
LCD_BLANK
LCD_ONLY
LCD_RST
LCD_SEG0[5:0]
LCD_SEG15[5:0]
LCD_SEGDIO16[5:0]
LCD_SEGDIO45[5:0]
to
to
2420[5:0] to
2410[5:0] to
240D[4:0]
243D[5:0]
Location Rst Wk Dir
2405[7:0]
2406[7:0]
2407[7:0]
2408[7:0]
2409[7:0]
240A[7:0]
240B[7:0]
2400[6:4]
241F[5:0]
240C[0]
240C[1]
28B2[6]
240C[2]
2400[7]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
0
–
–
–
© 2008–2011 Teridian Semiconductor Corporation
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W
Description
The LCD contrast DAC. This DAC controls the VLCD voltage and has an output range of
2.65 V to 5.3 V. The VLCD voltage is
Thus, the LSB of the DAC is 85.5 mV. The maximum DAC output voltage is limited by
V3P3SYS, VBAT, and whether LCD_BSTE = 1.
Enables the LCD display. When disabled, VLC2, VLC1, and VLC0 are ground as are
the COM and SEG outputs if their LCD_MAP bit is 1.
Enables LCD segment driver mode of combined SEGDIO pins. Pins that cannot be
configured as outputs (SEG48 through SEG50) become inputs with internal pull ups
when their LCD_MAP bit is zero. Also, note that SEG48 through SEG50 are multiplexed
with the in-circuit emulator signals. When the ICE_E pin is high, the ICE interface is
enabled, and SEG48 through SEG50 become E_RXTX, E_TCLK and E_RST,
respectively.
Selects the LCD bias and multiplex mode.
Turns on or off all LCD segments without changing LCD data. If both bits are set, the
LCD display is turned on.
Puts the 71M6543 to sleep, but with LCD display still active. Ignored if system power is
present. It awakens when the Wake Timer times out, when certain DIO pins are raised,
or when system power returns (see
Clear all bits of LCD data. These bits affect SEGDIO pins that are configured as LCD
drivers. This bit does not auto clear.
SEG Data for SEG0 through SEG15. DIO data for these pins is in SFR space.
SEG and DIO data for SEGDIO16 through SEGDIO45. If configured as DIO, bit 1 is
direction (1 is output, 0 is input), bit 0 is data, and the other bits are ignored.
LCD_MODE
000
001
010
011
100
101
110
4 states, 1/3 bias
3 states, 1/3 bias
2 states, 1/2 bias
3 states, 1/2 bias
5 states, 1/3 bias
6 states, 1/3 bias
Static display
Output
VLCD = 2.65 + 2.65 * LCD_DAC[4:0]/31
3.2 Battery
Modes).
v1.2