71M6545 MAXIM [Maxim Integrated Products], 71M6545 Datasheet - Page 82

• Manufacturer Part Number: 71M6545
• Description: Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size
• Manufacturer: MAXIM [Maxim Integrated Products]

Data Sheet 71M6545/H
5
5.1
In
Unimplemented bits have no memory storage, writing them has no effect, and reading them always returns zero. Reserved bits are identified with
an ‘R’, and must always be written with a zero. Writing values other than zero to reserved bits may have undesirable side effects and must be
avoided. Non-volatile bits are shaded in dark gray. Non-volatile bits are backed-up during power failures if the system includes a battery connected
to the VBAT_RTC pin and the pin voltage is within specification.
The I/O RAM locations listed in
I/O RAM locations are usually modified only at boot-up. The addresses shown in
from
0x2106[7:5].
82
Table 59
RTMUX
DIO_R5
DIO_R4
DIO_R3
FOVRD
MUX5
MUX4
MUX3
MUX2
MUX1
MUX0
TEMP
Name
RCE0
Table 60
CE6
CE5
CE4
CE3
CE2
CE1
CE0
FIRMWARE INTERFACE
I/O RAM Map –Functional Order
and
which are used throughout this document. For instance, EQU[2:0] can be accessed at I/O RAM 0x2000[7:5] or at I/O RAM
200C
200D
201C
201D
Table
Addr
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
200A
200B
200E
200F
2010
201B
60, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits are identified with a ‘U’.
DIFF6_E
Bit 7
U
U
U
U
U
U
R
Table 59
CHOPR[1:0]
Table 59: I/O RAM Map – Functional Order, Basic Configuration
EQU[2:0]
TEMP_PWR
have sequential addresses to facilitate reading by the MPU (e.g., in order to verify their contents). These
DIFF4_E
Bit 6
U
U
U
U
MUX_DIV[3:0]
© 2008–2011 Teridian Semiconductor Corporation
MUX9_SEL
MUX7_SEL
MUX5_SEL
MUX3_SEL
MUX1_SEL
TMUXR4[2:0]
DIO_R11[2:0]
DIO_R9[2:0]
OSC_COMP
DIFF2_E
RMT6_E
Bit 5
U
R
TEMP_BAT
DIFF0_E
RMT4_E
Bit 4
PLS_MAXWIDTH[7:0]
PLS_INTERVAL[7:0]
U
SUM_SAMPS[7:0]
U
U
Table 59
RFLY_DIS
RMT2_E
Bit 3
are an alternative sequential address to the addresses
U
U
U
U
U
U
CHOP_E[1:0]
CE_LCTN[5:0]
SUM_SAMPS[12:8]
Bit 2
U
FIR_LEN[1:0]
MUX10_SEL
MUX8_SEL
MUX6_SEL
MUX4_SEL
MUX2_SEL
MUX0_SEL
TEMP_PER[2:0]
DIO_RPB[2:0]
TMUXR6[2:0]
TMUXR2[2:0]
DIO_R10[2:0]
DIO_R8[2:0]
RTM_E
Bit 1
U
PDS_6545_009
PLS_INV
CE_E
Bit 0
U
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