PT7A4410J ETC1 [List of Unclassifed Manufacturers], PT7A4410J Datasheet

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PT7A4410J

Manufacturer Part Number
PT7A4410J
Description
T1/E1/OC3 System Synchronizer
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
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PT0106(09/02)
Features
• Supports AT&T TR62411 Stratum 3, 4 and
• Supports ITU-T G.812 Type IV clocks for
Applications
• Synchronization and timing control for multitrunk
Stratum 4 Enhanced for DS1 interfaces and for
ETSI ETS 300 011, TBR 4, TBR 12, and TBR
13 for E1 interfaces
1.544kbit/s interfaces and 2.048kbit/s interface
Provides C1.5, C3, C2, C4, C8, C6, C16 and C19
output clock signals
Provides five kinds of 8kHz ST-BUS framing
signals
Two independent reference inputs
Input reference frequency 1.544MHz, 2.048MHz
or 8kHz selectable
Provides bit error free reference switching and
meets phase slope and MTIE requirements
Normal, Holdover or Free-Run operating modes
available
Holdover accuracy: ±0.2ppm
Automatic reference input impairment monitor
Power supply: 5V (4410) and 3.3V(4410L)
T1 and E1 systems, STS-3/OC3 systems
ST-BUS clock and frame pulse sources
Primary Trunk Rate Converters
1
Introduction
PT7A4410/4410L employs a digital phase-locked
loop (DPLL) to provide timing and synchronizing
signals for multitrunk T1 and E1 primary rate
transmission links, and for STS-3/OC3 links. The ST-
BUS clock and framing signals are phase-locked to
input reference signals of either 2.048 MHz,
1.544MHz or 8 kHz.
The PT7A4410/4410L meets the requirements for
AT&T TR62411 Stratum 3, 4 and Stratum 4 En-
hanced, and ETSI ETS 300 011 in jitter tolerance,
jitter transfer, intrinsic jitter, frequency accuracy, hold-
over accuracy, capture range, phase slope and MTIE,
etc.
The PT7A4410/4410L operates in Manual or Auto-
matic Mode, and in each of the modes, three operat-
ing states are available: Normal, Holdover and Free-
Run.
Ordering Information
P
P
P
P
P
P
T1/E1/OC3 System Synchronizer
P
a
a
a
a
a
T
T
t r
t r
t r
t r
t r
7
7
A
N
N
N
A
N
N
4 4
4
u
u
u
u
u
1 4
m
m
m
m
m
0 1
b
b
b
b
b
J 0
J L
r e
r e
r e
r e
r e
PT7A4410/4410L
4 4
4 4
P
P
P
P
P
P -
P -
Data Sheet
c a
c a
c a
c a
c a
n i
n i
a k
a k
a k
a k
a k
P
P
e g
e g
e g
L
L
e g
e g
C
C
C
C
Ver:0

Related parts for PT7A4410J

PT7A4410J Summary of contents

Page 1

Features • Supports AT&T TR62411 Stratum 3, 4 and Stratum 4 Enhanced for DS1 interfaces and for ETSI ETS 300 011, TBR 4, TBR 12, and TBR 13 for E1 interfaces • Supports ITU-T G.812 Type IV clocks for ...

Page 2

Features ....................................................................................................................................................... 1 Applications ................................................................................................................................................ 1 Introduction ................................................................................................................................................. 1 Ordering Information .................................................................................................................................. 1 Block Diagram ............................................................................................................................................ 3 Pin Information ........................................................................................................................................... 4 Pin Assignment ..................................................................................................................................... 4 Pin Configuration ................................................................................................................................. 4 Pin Description ..................................................................................................................................... 5 Functional Description ................................................................................................................................ 7 Overall Operation ...

Page 3

Block Diagram Figure 1. Block Diagram RST OSCi Master Clock OSCo TCK TDI IEEE 1149.1a TMS TRST TDO PRI Reference TIE Select MUX SEC Correct Enable RSEL Mode/State LOS1 Control Machine LOS2 MS1 HOLDOVER PT0106(09/02) T1/E1/OC3 System Synchronizer V ...

Page 4

Pin Information Pin Assignment Table 1. Pin Assignment ...

Page 5

Pin Description Table 2. Pin Description ...

Page 6

Table 2. Pin Description (continued ...

Page 7

Functional Description Overall Operation The PT7A4410/4410L is a multitrunk synchronizer that pro- vides the clock and frame signals for T1 and E1 primary rate digital transmission links, and STS-3/OC3 links. It basically consists of the Clock Generator, Mode/State Con- ...

Page 8

Whenever there is a change in the input reference source, such as a switch from the primary reference signal (PRI) to second- ary reference signal (SEC), the typical result is a step change in phase of the DPLL input ...

Page 9

The Control Circuit uses signals from the State Machine and Input Impairment Monitor to control the operating states of the DPLL. Three states are available, Normal, Holdover and Free-Run. The Error Signal, after limited and filtered, is sent to ...

Page 10

Mode/State Control Machine The Mode/State Control Machine determines whether the PT7A4410/4410L operates in Automatic or Manual mode, and whether the Normal, Holdover or Free-Run state. In Automatic Mode, the PT7A4410/4410L selects one of three states, Normal, ...

Page 11

Manual Mode The Manual Operation Mode is used when either very simple control is required, or when complex control is required which is not accommodated by Automatic Mode. For example, Manual Mode can be used in a system requiring ...

Page 12

Table 6. Manual Operation Mode ...

Page 13

Table 7. Automatic Operation Mode (MS1 MS2=11, RSEL= ...

Page 14

Applications Information Master Clock The PT7A4410/4410L uses either an external clock source or an external crystal as the master timing source. In Free-Run State, the frequency tolerance of the PT7A4410/ 4410L output clocks are equal to the frequency tolerance ...

Page 15

A simple way to control the Guard Time is shown in Figure 11. The Guard Time can be calculated as follows 0 SIH ...

Page 16

Reset Circuit A simple power up reset circuit with about reset active (low) time is shown in Figure 14. Resistor R only. The reset low time is not critical but should be greater than 300ns. Figure ...

Page 17

T1o T1i 1UIT1 644ns E1o T1o T1o 1UIE1 488ns Using ...

Page 18

Absolute Maximum Ratings Storage Temperature ...................................................... -65 Ambient Temperature with Power Applied ...................... -40 Supply Voltage to Ground Potential (Inputs & V Supply Voltage to Ground Potential (Outputs & D/O Only) .. -0.3 to 7.0V DC Input Voltage .................................................................. ...

Page 19

DC Electrical and Power Supply Characteristics Table 9. DC Electrical and Power Supply Characteristics ...

Page 20

AC Electrical Characteristics Performance Table 10. Performance ...

Page 21

Voltage Levels for Timing Parameter Measurement Table 11. Voltage Levels for Timing Parameter Measurement ...

Page 22

Input and Output Timing Table 12. Input and Output Timing of 4409 ...

Page 23

Table 13. Input and Output Timing of 4409L ...

Page 24

Table 14. Input and Output Timing (Continued ...

Page 25

Figure 18. Output Timing F8 F0 F16 C16 C3W C3 C1 C19 Figure 19. Output Timing F8 C2 RSP TSP PT0106(09/02) T1/E1/OC3 System Synchronizer t F0WL t C16WL t t C8W C8W t ...

Page 26

Figure 20. Setup and Hold Timing of Input Controls F8 MS1,2 LOS1,2 RSEL GTi Intrinsic Jitter Unfiltered Table 15. Intrinsic Jitter Unfiltered ...

Page 27

C1.5 (1.544MHz) Instrinsic Jitter Filtered Table 16. C1.5 (1.544MHz) Instrinsic Jitter Filtered ...

Page 28

Input to 8kHz Output Jitter Transfer Table 18. 8kHz Input to 8kHz Output Jitter Transfer ...

Page 29

Input to 2.048MHz Output Jitter Transfer Table 20. 2.048MHz Input to 2.048MHz Output Jitter Transfer ...

Page 30

Input Jitter Tolerance Table 21. 8kHz Input Jitter Tolerance ...

Page 31

Input Jitter Tolerance Table 23. 2.048MHz Input Jitter Tolerance ...

Page 32

Notes: 1. Voltages are with respect to ground (GND) unless otherwise stated. 2. Supply voltage and operation temperature are as per Recommended Operating Conditions. 3. Timing parameters are as per AC Electrical Characteristics - Voltage Levels for Timing Parameter ...

Page 33

Mechanical Specifications Figure 21. 44-pin PLCC PT0106(09/02) PT7A4410/4410L T1/E1/OC3 System Synchronizer 33 Data Sheet Ver:0 ...

Page 34

Email: support@pti.com.cn China: No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Asia Pacific: Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 U.S.A.: 2380 Bering Drive, San ...

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