PT7A4410J ETC1 [List of Unclassifed Manufacturers], PT7A4410J Datasheet - Page 9

• Manufacturer Part Number: PT7A4410J
• Description: T1/E1/OC3 System Synchronizer
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

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The Control Circuit uses signals from the State Machine and
Input Impairment Monitor to control the operating states of
the DPLL. Three states are available, Normal, Holdover and
Free-Run.
The Error Signal, after limited and filtered, is sent to Digitally
Controlled Oscillator. Based on the processed error value, the
DCO will generate the corresponding digital output signals
for the Tapped Delay Line in the Output Interface Circuit to
produce 12.352MHz, 12.624MHz, 19.44MHz and 16.384MHz
signals. The DCO synchronization method depends upon the
PT7A4410/4410L operating state, as follows:
In Normal state, the DCO generates four output signals which
are frequency and phase locked to the selected input reference
signal.
In Holdover state, the DCO generates four output signals whose
frequencies are equal to what they were for a 30ms period
shortly before the end of the last Normal State.
In Free-Run state, the DCO is free running with an accuracy
equal to that of the OSCi 20MHz source.
Output Interface Circuit
The Output Interface Circuit consists of the Tapped Delay Lines
and E1/T1 Dividers as shown in Figure 5.
PT0106(09/02)
Figure 5. Block Diagram of Output Interface Circuit
A C K i
Signal
From
DCO
Delay Line
Tapped
Tapped
Tapped
Tapped
Delay
Delay
Delay
Line
Line
Line
APLL
12.352MHz
16.384MHz
12.624MHz
19.44MHz
9
Signals from the DCO are sent to Tapped Delay Lines to gener-
ate four clock signals, 16.384MHz, 12.624MHz, 19.44MHz
and 12.352MHz, which are divided in the T1 and E1 Dividers
respectively to provide needed clock and frame signals.
The T1 Divider uses the 12.352MHz signal to generate two
clock signals, C1.5 and C3. They have a nominal 50% duty
cycle.
The DS2 Divider uses 12.624MHz signal to generate clock
signal C6.
Clock signal C19 is generated from 19.44MHz by tapped De-
lay Line.
The E1 Divider uses the 16.384MHz signal to generate four
clock signals and three frame signals, i.e., C2, C4, C8, C16,
F0, F8 and F16. The frame signals are generated directly from
the C16 signal.
The C2, C4, C8 and C16 signals have nominal 50% duty cycle.
All the frame and clock outputs are locked to each other for all
operating states. They have limited driving capability and
should be buffered when driving high capacitance (e.g., 30pF)
loads.
T1/E1/OC3 System Synchronizer
Divider
Divider
Divider
DS2
T1
E1
C1.5
C3
C 2
C 4
C 8
C 1 6
F 0
F 8
F 1 6
R S P
T S P
A C K o
C 1 9
C 6
PT7A4410/4410L
Data Sheet
Ver:0