WM8731L WOLFSON [Wolfson Microelectronics plc], WM8731L Datasheet - Page 38

• Manufacturer Part Number: WM8731L
• Description: Portable Internet Audio CODEC with Headphone Driver and Programmable Sample Rates
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

WM8731 / WM8731L
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To accommodate system timing requirements the interpretation of BCLK maybe inverted, this is
controlled vias the software shown in Table 15. This is especially appropriate for DSP mode.
ADCDAT lines are always outputs. They power up and return from standby low.
DACDAT is always an input. It is expected to be set low by the audio interface controller when the
WM8731/L is powered off or in standby.
ADCLRC, DACLRC and BCLK can be either outputs or inputs depending on whether the device is
configured as a master or slave. If the device is a master then the DACLRC and BCLK signals are
outputs that default low. If the device is a slave then the DACLRC and BCLK are inputs. It is
expected that these are set low by the audio interface controller when the WM8731/L is powered off
or in standby.
Table 15 Digital Audio Interface Control
Note: If right justified 32 bit mode is selected then the WM8731/L defaults to 24 bits.
0000111
Digital Audio
Interface
Format
REGISTER
ADDRESS
1:0
3:2
4
5
6
7
BIT
FORMAT[1:0]
IWL[1:0]
LRP
LRSWAP
MS
BCLKINV
LABEL
10
10
0
0
0
0
DEFAULT
Audio Data Format Select
11 = DSP Mode, frame sync + 2
data packed words
10 = I
justified
01 = MSB-First, left justified
00 = MSB-First, right justified
Input Audio Data Bit Length Select
11 = 32 bits
10 = 24 bits
01 = 20 bits
00 = 16 bits
DACLRC phase control (in left, right
or I
1 = Right Channel DAC data when
DACLRC high
0 = Right Channel DAC data when
DACLRC low
(opposite phasing in I
or
DSP mode A/B select (in DSP mode
only)
1 = MSB is available on 2nd BCLK
rising edge after DACLRC rising
edge
0 = MSB is available on 1st BCLK
rising edge after DACLRC rising
edge
DAC Left Right Clock Swap
1 = Right Channel DAC Data Left
0 = Right Channel DAC Data Right
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Bit Clock Invert
1 = Invert BCLK
0 = Don’t invert BCLK
2
S modes)
2
S Format, MSB-First left-1
DESCRIPTION
PD Rev 4.3 August 2006
2
S mode)
Production Data
38