WM9712CLGEFL/RV WOLFSON [Wolfson Microelectronics plc], WM9712CLGEFL/RV Datasheet - Page 19

• Manufacturer Part Number: WM9712CLGEFL/RV
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

Production Data
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AUDIO ADC
The WM9712L has a stereo sigma-delta ADC to digitize audio signals. The ADC achieves high quality
audio recording at low power consumption. The ADC sample rate can be controlled by writing to a
control register (see “Variable Rate Audio”). It is independent of the DAC sample rate.
To save power, the left and right ADCs can be separately switched off using the PD11 and PD12 bits,
whereas PR0 disables both ADCs (see “Power Management” section). If only one ADC is running, the
same ADC data appears on both the left and right AC-Link slots.
HIGH PASS FILTER
The WM9712L audio ADC incorporates a digital high-pass filter that eliminates any DC bias from the
ADC output data. The filter is enabled by default. For DC measurements, it can be disabled by writing
a ‘1’ to the HPF bit (register 5Ch, bit 3).
ADC SLOT MAPPING
By default, the output of the left audio ADC appears on slot 3 of the SDATAIN signal (pin 8), and the
right ADC data appears on slot 4. However, the ADC output data can also be sent to other slots, by
setting the ASS (ADC slot select) control bits as shown below.
Table 6 ADC Control
REGISTER
ADDRESS
5Ch
Additional
Function
Control
BIT
1:0
3
LABEL
ASS
HPF
DEFAULT
00
0
DESCRIPTION
ADC to slot mapping
00: Left = Slot 3, Right = Slot 4 (default)
01: Left = Slot 7, Right = Slot 8
10: Left = Slot 6, Right = Slot 9
11: Left = Slot 10, Right = Slot 11
High-pass filter disable
0: Filter enabled (for audio)
1: Filter disabled (for DC measurements)
PD, Rev 4.6, November 2011
WM9712L
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