WM9714L_06 WOLFSON [Wolfson Microelectronics plc], WM9714L_06 Datasheet - Page 16

• Manufacturer Part Number: WM9714L_06
• Description: AC 97 Audio CODEC
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

WM9714L
PLL MODE
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INTERNAL CLOCK FREQUENCIES
The internal clock frequencies are defined as follows (refer to Figure 2):
Table 3 Clock Division Mode Table
AUXADC
The clock for the AUXADC nominally runs at 768kHz and is derived from BITCLK. The divisor for the
clock generator is set by PENDIV. This enables the AUXADC clock frequency to be set according to
power consumption and conversion rate considerations.
The PLL operation is controlled by register 46h (see Table 4) and has two modes of operation:
The PLL has been optimized for nominal input clock (PLL_IN) frequencies in the range 8.192MHz –
19.661MHz (LF=0) and 2.048MHz – 4.9152MHz (LF=1).
Through use of a clock divider (div by 2 / 4) on the input to the PLL frequencies up to 78.6MHz can
be accommodated. The input clock divider is enabled by DIVSEL (0=Off) and the division ratio is set
by DIVCTL (0=div2, 1=div4).
Figure 3 PLL Architecture
8ks/s voice and HIFI
8ks/s voice only (power save)
16ks/s voice and HIFI
16ks/s voice only (power save)
32ks/s voice and HIFI
48ks/s voice and HIFI
AC97 CLK – nominally 24.576MHz, used to generate AC97 BITCLK at 12.288MHz.
HIFI CLK – for HIFI playback at 48ks/s HIFI CLK = 24.576MHz. See Table 3 for voice only
playback.
Voice DAC CLK – see Table 3 for sample rate vs clock frequency.
SAMPLE RATE
Integer N
Fractional N
2.048MHz
2.048MHz
4.096MHz
4.096MHz
8.192MHz
12.288MHz
VOICE DAC CLK
FREQUENCY
24.576MHz
4.096MHz
24.576MHz
8.192MHz
24.576MHz
24.576MHz
FREQUENCY
HIFI CLK
PP Rev 3.0 June 2006
Pre-Production
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