A3P015-1FG144 ACTEL [Actel Corporation], A3P015-1FG144 Datasheet
A3P015-1FG144
Related parts for A3P015-1FG144
A3P015-1FG144 Summary of contents
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... Six chip (main) and three quadrant global networks are available for A3P060 and above. 4. For higher densities and support of additional features, refer to the 5. The M1A3P250 device does not support this package. † A3P015 and A3P030 devices do not support this feature. February 2008 © 2008 Actel Corporation ® ...
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... I/Os Per Package ProASIC3 Devices A3P015 A3P030 ARM7 Devices Cortex-M1 Devices Package QN68 49 – QN132 – 81 VQ100 – 77 TQ144 – – PQ208 – – FG144 – – FG256 – – FG484 – – Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the handbook to ensure complying with design and board migration requirements ...
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... FG Package Type Speed Grade F = 20% Slower than Standard* Blank = Standard 1 = 15% Faster than Standard 2 = 25% Faster than Standard Part Number ProASIC3 Devices A3P015 = 15,000 System Gates A3P030 = 30,000 System Gates A3P060 = 60,000 System Gates A3P125 = 125,000 System Gates A3P250 = 250,000 System Gates ...
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... References made to ProASIC3 devices also apply to ARM-enabled ProASIC3 devices. The ARM-enabled part numbers start with M7 (CoreMP7) and M1 (Cortex-M1). Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx. A3P015 and A3P030 The A3P015 and A3P030 are architecturally compatible; there are no RAM or PLL features A3P060 A3P125 ...
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... ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). The A3P015 and A3P030 devices have no PLL or RAM support. ProASIC3 devices have million system gates, supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os. ...
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ProASIC3 Device Family Overview Security, built into the FPGA fabric inherent component of the ProASIC3 family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive ...
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... Advanced I/O structure ISP AES User Nonvolatile Decryption* * Not supported by A3P015 and A3P030 devices Figure 1-1 • ProASIC3 Device Architecture Overview with Two I/O Banks (A3P015, A3P030, A3P060, and A3P125) † The A3P015 and A3P030 do not support PLL or SRAM. † † Bank 0 Charge Pumps ...
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ProASIC3 Device Family Overview ISP AES User Nonvolatile Decryption FlashROM Figure 1-2 • ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P600, and A3P1000) The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as ...
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... The FlashROM is written using the standard ProASIC3 IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks (except in the A3P015 and A3P030 devices security keys stored in the FlashROM for a user design. ...
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... PLL and CCC ProASIC3 devices provide designers with very flexible clock conditioning capabilities. Each member of the ProASIC3 family contains six CCCs. One CCC (center west side) has a PLL. The A3P015 and A3P030 devices do not have a PLL. The six CCC blocks are located at the four corners and the centers of the east and west sides. ...
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... This document was updated to include A3P015 device information. QN68 is a (January 2008) new package that was added because it is offered in the A3P015. The following sections were updated: "Features and Benefits" "ProASIC3 Ordering Information" "Temperature Grade Offerings" ...
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ProASIC3 Device Family Overview Previous Version v2.1 The M7 and M1 device part numbers have been updated in Table 1 • ProASIC3 (May 2007) Product Family, "I/Os Per Package", "Automotive ProASIC3 Ordering Information", "Temperature Grade Offerings", and "Speed Grade and ...
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... Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definition of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information ...
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ProASIC3 DC and Switching Characteristics General Specifications DC and switching characteristics for –F speed grade targets are based only on simulation. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some ...
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ProASIC3 DC and Switching Characteristics Table 2-2 • Recommended Operating Conditions Symbol T Ambient temperature core supply voltage CC V JTAG DC voltage JTAG V Programming voltage PUMP V Analog power supply (PLL) CCPLL 2 ...
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Table 2-4 • Overshoot and Undershoot Limits Average V V and VMV Duration as a Percentage of Clock Cycle CCI 2 less 3 V 3.3 V 3.6 V Notes: 1. Based on reliability requirements at 85°C. 2. The ...
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ProASIC3 DC and Switching Characteristics Power-Up/-Down Behavior of Low-Power Flash Devices on clock and lock recovery. Internal Power-Up Activation Sequence 1. Core 2. Input buffers Output buffers, after 200 ns delay from input buffer activation where ...
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Thermal Characteristics Introduction The temperature variable in the Actel Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ...
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... V = 1.425 Junction Temperature (°C) –40°C 0°C 25°C 0.87 0.92 0.95 0.83 0.88 0.90 0.80 0.85 0.87 A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000 and VMV currents. Values do not include I/O static contribution, PUMP ...
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Table 2-9 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings Applicable to Standard Plus I/O Banks Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) ...
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ProASIC3 DC and Switching Characteristics Table 2-11 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings Applicable to Advanced I/O Banks Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS ...
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Table 2-13 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings Applicable to Standard I/O Banks C (pF) LOAD Single-Ended 3.3 V LVTTL / 35 3.3 V LVCMOS 2.5 V LVCMOS 35 1.8 V LVCMOS ...
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ProASIC3 DC and Switching Characteristics Power Consumption of Various Internal Resources Table 2-14 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices Parameter Definition P Clock contribution of a Global Rib AC1 P Clock contribution of a Global ...
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Table 2-15 • Different Components Contributing to the Static Power Consumption in ProASIC3 Devices Definition Parameter P Array static power in Active mode DC1 P I/O input pin static power (standard-dependent) DC2 P I/O output pin static power (standard-dependent) DC3 ...
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ProASIC3 DC and Switching Characteristics Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software. The power calculation ...
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Combinatorial Cells Contribution— C-CELL C-CELL the number of VersaTiles used as combinatorial modules in the design. C-CELL is the toggle rate of VersaTile outputs—guidelines are provided ...
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ProASIC3 DC and Switching Characteristics Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock percentage. If the toggle rate of a net is 100%, this means ...
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User I/O Characteristics Timing Model I/O Module (Registered 1. LVPECL D Q (Applicable to Advanced I/O Banks only 0.24 ns ICLKQ t = 0.26 ns ISUD Input LVTTL Clock Register Cell t = 0.76 ...
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ProASIC3 DC and Switching Characteristics t PY PAD DIN V PAD Y GND DIN GND Figure 2-3 • Input Buffer Timing Model and Delays (example CLK I/O Interface = MAX(t (R), t ...
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DOUT D Q CLK D From Array I/O Interface D DOUT PAD Figure 2-4 • Output Buffer Model and Delays (example) ProASIC3 DC and Switching Characteristics t DP DOUT t = MAX(t (R MAX(t ...
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ProASIC3 DC and Switching Characteristics t EOUT D Q CLK CLK D I/O Interface D 50 EOUT (R) 50% EOUT t ZL PAD V trip D 50 EOUT (R) 50% EOUT t ZLS ...
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Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-18 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Applicable to ...
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ProASIC3 DC and Switching Characteristics Table 2-21 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions DC I/O Standards 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V ...
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Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings –2 Speed Grade, Commercial-Case Conditions: T Worst Case V = 3.0 V CCI Advanced I/O Banks I/O Standard 3.3 V LVTTL / 12 High 35 3.3 V LVCMOS 2.5 V ...
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ProASIC3 DC and Switching Characteristics Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings –2 Speed Grade, Commercial-Case Conditions 3.0 V CCI Standard Plus I/O Banks I/O Standard 3.3 V LVTTL / 12 mA 3.3 V ...
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Detailed I/O DC Characteristics Table 2-27 • Input Capacitance Symbol Definition C Input capacitance IN C Input capacitance on the clock pin INCLK Table 2-28 • I/O Output Buffer Maximum Resistances Applicable to Advanced I/O Banks Standard 3.3 V LVTTL ...
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ProASIC3 DC and Switching Characteristics Table 2-29 • I/O Output Buffer Maximum Resistances Applicable to Standard Plus I/O Banks Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI/PCI-X Notes: ...
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Table 2-30 • I/O Output Buffer Maximum Resistances Applicable to Standard I/O Banks Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS Notes: 1. These maximum values are provided for informational reasons ...
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ProASIC3 DC and Switching Characteristics Table 2-32 • I/O Short Currents I Applicable to Advanced I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI/PCI-X * ...
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Table 2-33 • I/O Short Currents I OSH Applicable to Standard Plus I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI/PCI 100°C J Table 2-34 ...
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ProASIC3 DC and Switching Characteristics The length of time an I/O can withstand I reliability data below is based I/O setting, which is the worst case for this type of analysis. For example, at ...
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Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic (LVTTL general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-37 • Minimum and Maximum DC ...
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ProASIC3 DC and Switching Characteristics Table 2-39 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS V IL Drive Strength Min., V Max., V Min., V Max., V ...
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Timing Characteristics Table 2-41 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT –F 0.79 9.20 Std. 0.66 7.66 –1 0.56 ...
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ProASIC3 DC and Switching Characteristics Table 2-42 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT –F 0.79 12.32 Std. 0.66 ...
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Table 2-43 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT –F 0.79 8.65 Std. 0.66 7.20 –1 0.56 6.13 ...
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ProASIC3 DC and Switching Characteristics Table 2-44 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT –F 0.79 11.63 Std. ...
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Table 2-45 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Standard I/O Banks Drive Speed Strength Grade t DOUT 2 mA –F 0.79 Std. 0.66 –1 0.56 –2 0. –F 0.79 ...
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ProASIC3 DC and Switching Characteristics Table 2-46 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Standard I/O Banks Drive Speed Strength Grade t DOUT 2 mA –F 0.79 Std. 0.66 –1 0.56 –2 ...
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V LVCMOS Low-Voltage CMOS for 2 extension of the LVCMOS standard (JESD8-5) used for general- purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer. Table 2-47 • Minimum and Maximum ...
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ProASIC3 DC and Switching Characteristics Table 2-49 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 2.5 V LVCMOS V IL Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V ...
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Timing Characteristics Table 2-51 • 2.5 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT –F 0.72 10.41 Std. 0.60 8.66 –1 0.51 7.37 –2 0.45 6.47 ...
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ProASIC3 DC and Switching Characteristics Table 2-52 • 2.5 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT –F 0.72 13.69 Std. 0.60 11.40 –1 0.51 9.69 ...
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Table 2-53 • 2.5 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT –F 0.79 9.94 Std. 0.66 8.28 –1 0.56 7.04 –2 0.49 6.18 6 ...
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ProASIC3 DC and Switching Characteristics Table 2-54 • 2.5 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT –F 0.79 13.02 Std. 0.66 10.84 –1 0.56 ...
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Table 2-55 • 2.5 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Standard I/O Banks Drive Speed Strength Grade t DOUT 2 mA –F 0.79 Std. 0.66 –1 0.56 –2 0. –F 0.79 Std. 0.66 –1 0.56 ...
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ProASIC3 DC and Switching Characteristics Table 2-56 • 2.5 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Standard I/O Banks Drive Speed Strength Grade t DOUT 2 mA –F 0.79 Std. 0.66 –1 0.56 –2 0. –F ...
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V LVCMOS Low-voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-57 • Minimum and ...
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ProASIC3 DC and Switching Characteristics Table 2-59 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 1.8 V LVCMOS V IL Drive Strength Min., V Max –0.3 0. CCI 4 ...
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Timing Characteristics Table 2-61 • 1.8 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT –F 0.79 14.25 Std. 0.66 11.86 –1 0.56 10.09 –2 0.49 8.86 ...
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ProASIC3 DC and Switching Characteristics Table 2-62 • 1.8 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT –F 0.79 18.66 Std. 0.66 15.53 –1 0.56 13.21 ...
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Table 2-63 • 1.8 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT –F 0.79 13.61 Std. 0.66 11.33 –1 0.56 9.64 –2 0.49 8.46 4 ...
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ProASIC3 DC and Switching Characteristics Table 2-64 • 1.8 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t DOUT 2 mA –F 0.79 17.78 Std. 0.66 14.80 –1 0.56 12.59 –2 ...
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Table 2-66 • 1.8 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Standard I/O Banks Drive Speed Strength Grade t t DOUT 2 mA –F 0.79 18.03 Std. 0.66 15.01 –1 0.56 12.77 –2 0.49 11. –F ...
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ProASIC3 DC and Switching Characteristics Table 2-68 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 1.5 V LVCMOS V IL Drive Strength Min., V Max., V Min., V Max –0.3 ...
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Timing Characteristics Table 2-71 • 1.5 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT –F 0.79 10.05 Std. 0.66 8.36 –1 0.56 7.11 –2 0.49 6.24 ...
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ProASIC3 DC and Switching Characteristics Table 2-72 • 1.5 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t DOUT 2 mA –F 0.79 Std. 0.66 –1 0.56 –2 0. –F ...
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Table 2-73 • 1.5 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT –F 0.79 9.41 Std. 0.66 7.83 –1 0.56 6.66 –2 0.49 5.85 4 ...
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ProASIC3 DC and Switching Characteristics Table 2-75 • 1.5 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Standard I/O Banks Drive Speed Strength Grade t DOUT 2 mA –F 0.79 Std. 0.66 –1 0.56 –2 0.49 Notes: 1. Software ...
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AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is described in Table 2-78. Table 2-78 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH ( Measuring point = ...
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ProASIC3 DC and Switching Characteristics Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by Actel Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also ...
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Table 2-81 • LVDS Minimum and Maximum DC Input and Output Levels DC Parameter Description V Supply Voltage CCI V Output Low Voltage OL V Output High Voltage Output Lower Current Output High Current ...
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ProASIC3 DC and Switching Characteristics B-LVDS/M-LVDS Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Actel LVDS ...
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LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The full implementation of the ...
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ProASIC3 DC and Switching Characteristics I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Preset Data C Enable B CLK A Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered Figure 2-14 ...
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Table 2-87 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output Data Register OHD t Enable ...
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ProASIC3 DC and Switching Characteristics Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear Data CC Enable BB CLK AA CLR DD Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered Figure 2-15 • Timing ...
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Table 2-88 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output Data Register OHD t Enable ...
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ProASIC3 DC and Switching Characteristics Input Register 50% CLK 50% 1 Data Enable 50% t IHE t Preset ISUE Clear Out_1 Figure 2-16 • Input Register Timing Diagram Timing Characteristics Table 2-89 • Input Data Register Propagation Delays Commercial-Case Conditions: ...
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Output Register 50% 50% CLK t 1 50% Data_out Enable 50% t OHE t Preset OSUE Clear DOUT Figure 2-17 • Output Register Timing Diagram Timing Characteristics Table 2-90 • Output Data Register Propagation Delays Commercial-Case Conditions: T Parameter t ...
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ProASIC3 DC and Switching Characteristics Output Enable Register 50% CLK 1 50% D_Enable 50% Enable t t OESUE OEHE Preset Clear EOUT Figure 2-18 • Output Enable Register Timing Diagram 50% 50% 50 OESUD OEHD ...
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Timing Characteristics Table 2-91 • Output Enable Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Output Enable Register OECLKQ t Data Setup Time for the Output Enable Register OESUD t Data Hold Time for the Output Enable ...
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ProASIC3 DC and Switching Characteristics DDR Module Specifications Input DDR Module INBUF Data CLK CLKBUF CLR INBUF Figure 2-19 • Input DDR Timing Model Table 2-92 • Parameter Definitions Parameter Name t Clock-to-Out Out_QR DDRICLKQ1 t Clock-to-Out Out_QF DDRICLKQ2 t ...
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CLK Data 1 2 CLR t DDRIREMCLR t DDRICLR2Q1 Out_QF t DDRICLR2Q2 Out_QR Figure 2-20 • Input DDR Timing Diagram Timing Characteristics Table 2-93 • Input DDR Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Out Out_QR for Input DDR DDRICLKQ1 ...
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ProASIC3 DC and Switching Characteristics Output DDR Module Data_F (from core) CLK CLKBUF Data_R (from core) CLR INBUF Figure 2-21 • Output DDR Timing Model Table 2-94 • Parameter Definitions Parameter Name t Clock-to-Out DDROCLKQ t Asynchronous Clear-to-Out DDROCLR2Q t ...
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CLK Data_F DDROREMCLR Data_R CLR DDROREMCLR t DDROCLR2Q Out Figure 2-22 • Output DDR Timing Diagram Timing Characteristics Table 2-95 • Output DDR Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Out of DDR for ...
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ProASIC3 DC and Switching Characteristics VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer ...
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50 50% OUT GND t PD (RR OUT t PD (RF) Figure 2-24 • Timing Model and Waveforms ProASIC3 DC and Switching Characteristics t PD NAND2 or Y Any Combinatorial Logic ...
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ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-96 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: T Combinatorial Cell Equation INV AND2 · B NAND2 Y = !(A · B) OR2 ...
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CLK t SUD 50% Data EN 50 PRE SUE CLR Out t CLKQ Figure 2-26 • Timing Model and Waveforms Timing Characteristics Table 2-97 • Register Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the ...
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ProASIC3 DC and Switching Characteristics Global Resource Characteristics A3P250 Clock Tree Topology Clock delays are device-specific. The global tree presented in device used to drive all D-flip-flops in the device. CCC Figure 2-27 • Example of Global Tree ...
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... CCC module. For more details on clock conditioning capabilities, refer to the Table 2-105 on page 2-82 Minimum and maximum delays are measured with minimum and maximum loading. Timing Characteristics Table 2-98 • A3P015 Global Resource Commercial-Case Conditions: T Parameter Description t Input LOW Delay for Global Clock ...
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ProASIC3 DC and Switching Characteristics Table 2-100 • A3P060 Global Resource Commercial-Case Conditions: T Parameter Description t Input LOW Delay for Global Clock RCKL t Input HIGH Delay for Global Clock RCKH t Minimum Pulse Width HIGH for Global Clock ...
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Table 2-102 • A3P250 Global Resource Commercial-Case Conditions: T Parameter Description t Input LOW Delay for Global Clock RCKL t Input HIGH Delay for Global Clock RCKH t Minimum Pulse Width HIGH for Global Clock RCKMPWH t Minimum Pulse Width ...
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ProASIC3 DC and Switching Characteristics Table 2-104 • A3P600 Global Resource Commercial-Case Conditions: T Parameter Description t Input LOW Delay for Global Clock RCKL t Input HIGH Delay for Global Clock RCKH t Minimum Pulse Width HIGH for Global Clock ...
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Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-106 • ProASIC3 CCC/PLL Specification Parameter Clock Conditioning Circuitry Input Frequency f Clock Conditioning Circuitry Output Frequency f 1 Serial Clock (SCLK) for Dynamic PLL Delay Increments in Programmable Delay Blocks ...
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ProASIC3 DC and Switching Characteristics Output Signal Note: Peak-to-peak jitter measurements are defined by T Figure 2-28 • Peak-to-Peak Jitter Definition period_max period_min = T – T peak-to-peak period_max period_min v1.3 . ...
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Embedded SRAM and FIFO Characteristics SRAM ADDRA11 ADDRA10 ADDRA0 DINA8 DINA7 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB11 ADDRB10 ADDRB0 DINB8 DINB7 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB Figure 2-29 • RAM Models ProASIC3 DC and ...
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ProASIC3 DC and Switching Characteristics Timing Waveforms CLK ADD t BKS BLK_B t ENS WEN_B Figure 2-30 • RAM Read for Pass-Through Output CLK ADD t BKS BLK_B t ENS WEN_B ...
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CYC t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-32 • RAM Write, Output Retained (WMODE = 0) t CKH CLK ...
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ProASIC3 DC and Switching Characteristics CLK1 ADD1 DI1 CLK2 WEN_B1 WEN_B2 ADD2 DI2 DO2 (pass-through) DO2 (pipelined) Figure 2-34 • Write Access after Write onto Same Address ...
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CLK1 ADD1 DI1 0 t WRO CLK2 WEN_B1 WEN_B2 A ADD2 DO2 D n (pass-through) DO2 D (pipelined) Figure 2-35 • Read Access after Write onto Same Address ProASIC3 ...
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ProASIC3 DC and Switching Characteristics CLK1 ADD1 WEN_B1 DO1 D n (pass-through) DO1 (pipelined) CLK2 ADD2 DI2 WEN_B2 Figure 2-36 • Write Access after Read onto Same Address CLK RESET_B Figure 2-37 • RAM Reset 2 -9 ...
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Timing Characteristics Table 2-107 • RAM4K9 Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t BLK_B setup time BKS t BLK_B hold ...
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ProASIC3 DC and Switching Characteristics Table 2-108 • RAM512X18 Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t Input data (DI) setup ...
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FIFO RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP AEVAL11 AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 WD16 WD0 WEN WBLK WCLK RPIPE Figure 2-38 • FIFO Model ProASIC3 DC and Switching Characteristics FIFO4K18 RD17 RD16 RD0 FULL ...
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ProASIC3 DC and Switching Characteristics Timing Waveforms RCLK/ WCLK RESET_B EMPTY AEMPTY FULL AFULL WA/RA (Address Counter) Figure 2-39 • FIFO Reset RCLK EMPTY AEMPTY WA/RA NO MATCH (Address Counter) Figure 2-40 • FIFO EMPTY Flag and AEMPTY Flag Assertion ...
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WCLK FULL AFULL WA/RA NO MATCH (Address Counter) Figure 2-41 • FIFO FULL Flag and AFULL Flag Assertion WCLK MATCH WA/RA NO MATCH (EMPTY) (Address Counter) 1st Rising Edge After 1st Write RCLK EMPTY AEMPTY Figure 2-42 • FIFO EMPTY ...
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ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-109 • FIFO (for all dies except A3P250) Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B ...
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Table 2-110 • FIFO (for A3P250 only, aspect-ratio-dependent) Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t Input Data (DI) Setup ...
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ProASIC3 DC and Switching Characteristics Table 2-111 • A3P250 FIFO 512×8 Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t Input ...
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Table 2-112 • A3P250 FIFO 1k×4 Worst Commercial-Case Conditions: T Parameter Description t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t Input Data (DI) Setup Time ...
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ProASIC3 DC and Switching Characteristics Table 2-113 • A3P250 FIFO 2k×2 Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t Input ...
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Table 2-114 • A3P250 FIFO 4k×1 Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t Input Data (DI) Setup Time DS ...
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ProASIC3 DC and Switching Characteristics Embedded FlashROM Characteristics t SU CLK t HOLD Address A 0 Data Figure 2-44 • Timing Diagram Timing Characteristics Table 2-115 • Embedded FlashROM Access Time Parameter t Address Setup Time SU t Address Hold ...
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JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the I/O Characteristics" section on page 2-15 Timing ...
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... TJ, Maximum Junction Temperature, was changed to 100° from 110º in the (June 2008) "Thermal Characteristics" section Power Allowed has thus changed to 1.463 W from 1.951 W. Values for the A3P015 device were added to Current Characteristics. Values for the A3P015 device were added to Contributing to Dynamic Power Consumption in ProASIC3 removed. Table 2-15 · ...
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Previous Version v1.0 In Table 2-106 · ProASIC3 CCC/PLL (continued) are new. Table 2-116 · JTAG 1532 in the previous version of the document. v2.2 This document was previously in datasheet v2. result of moving to the handbook ...
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ProASIC3 DC and Switching Characteristics Previous Version Advance v0 3-2, 150 was changed to 110 and the result changed from 3.9 to 1.951. (continued) Table 3-6 • Temperature and Voltage Derating Factors for Timing Delays was updated. Table ...
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Previous Version Advance v0.5 The "I/O Banks" section is new. This section explains the following types of I/Os: (continued) Advanced Standard+ Standard Table 2-12 • Automotive ProASIC3 Bank Types Definition and Differences is new. This table describes the standards listed ...
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ProASIC3 DC and Switching Characteristics Previous Version Advance v0.3 M7 device information is new. Table 2-4 • ProASIC3 Globals/Spines/Rows by Device was updated to include the number or rows in each top or bottom spine. EXTFB was removed from Figure ...
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Previous Version Advance v0.2 The "FIFO Flag Usage Considerations" section was updated. (continued) Table 2-13 was updated. Figure 2-24 was updated. The "Cold-Sparing Support" section is new. Table 2-43 was updated. Table 2-18 was updated. Pin descriptions in the "JTAG ...
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ProASIC3 DC and Switching Characteristics Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status datasheet may not have completed Actel’s qualification process. Actel may amend or enhance products during the product introduction ...
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Package Pin Assignments 48-Pin QFN Notes: 1. This is the bottom view of the package. 2. The die attach paddle center of the package is tied to ground (GND). Figure 3-1 • Note For Package Manufacturing and Environmental ...
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Package Pin Assignments 48-Pin QFP Pin Number A3P030 Function 1 IO82RSB1 2 GEC0/IO73RSB1 3 GEA0/IO72RSB1 4 GEB0/IO71RSB1 5 GND CCI 7 IO68RSB1 8 IO67RSB1 9 IO66RSB1 10 IO65RSB1 11 IO64RSB1 12 IO62RSB1 13 IO61RSB1 14 IO60RSB1 15 ...
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QFN Notes: 1. This is the bottom view of the package. 2. The die attach paddle center of the package is tied to ground (GND). Figure 3-2 • Note For Package Manufacturing and Environmental information, visit the Resource Center ...
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... IO51RSB1 GND CCI 27 IO50RSB1 28 IO48RSB1 29 IO46RSB1 30 IO44RSB1 31 IO42RSB1 32 TCK 33 TDI 34 TMS 35 V PUMP 36 TDO 3 -4 68-Pin QFN Pin Number A3P015 Function 37 TRST 38 V JTAG 39 IO40RSB0 40 IO37RSB0 41 GDB0/IO34RSB0 42 GDA0/IO33RSB0 43 GDC0/IO32RSB0 CCI 45 GND IO31RSB0 48 IO29RSB0 49 IO28RSB0 50 IO27RSB0 51 ...
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QFN Pin Number A3P030 Function 1 IO82RSB1 2 IO80RSB1 3 IO78RSB1 4 IO76RSB1 5 GEC0/IO73RSB1 6 GEA0/IO72RSB1 7 GEB0/IO71RSB1 GND CCI 11 IO68RSB1 12 IO67RSB1 13 IO66RSB1 14 IO65RSB1 15 IO64RSB1 16 ...
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Package Pin Assignments 132-Pin QFN D4 A36 B33 C30 C21 B23 A25 D3 Notes: 1. This is the bottom view of the package. 2. The die attach paddle center of the package is tied to ground (GND). Figure 3-3 • ...
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QFN Pin Number A3P030 Function A1 IO01RSB1 A2 IO81RSB1 IO80RSB1 A5 GEC0/IO77RSB1 GEB0/IO75RSB1 A8 IO73RSB1 A9 NC A10 V CC A11 IO71RSB1 A12 IO68RSB1 A13 IO63RSB1 A14 IO60RSB1 A15 NC A16 IO59RSB1 A17 ...
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Package Pin Assignments 132-Pin QFN Pin Number A3P030 Function C17 IO51RSB1 C18 NC C19 TCK C20 NC C21 V PUMP C22 V JTAG C23 NC C24 NC C25 NC C26 GDB0/IO38RSB0 C27 NC C28 V B0 CCI C29 IO32RSB0 C30 ...
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QFN Pin Number A3P060 Function A1 GAB2/IO00RSB1 A2 IO93RSB1 CCI A4 GFC1/IO89RSB1 A5 GFB0/IO86RSB1 A6 V CCPLF A7 GFA1/IO84RSB1 A8 GFC2/IO81RSB1 A9 IO78RSB1 A10 V CC A11 GEB1/IO75RSB1 A12 GEA0/IO72RSB1 A13 GEC2/IO69RSB1 A14 IO65RSB1 A15 V ...
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Package Pin Assignments 132-Pin QFN Pin Number A3P060 Function C17 IO57RSB1 C18 NC C19 TCK C20 VMV1 C21 V PUMP C22 V JTAG C23 V B0 CCI C24 NC C25 NC C26 GCA1/IO42RSB0 C27 GCC0/IO39RSB0 C28 V B0 CCI C29 ...
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QFN Pin Number A3P125 Function A1 GAB2/IO69RSB1 A2 IO130RSB1 CCI A4 GFC1/IO126RSB1 A5 GFB0/IO123RSB1 A6 V CCPLF A7 GFA1/IO121RSB1 A8 GFC2/IO118RSB1 A9 IO115RSB1 A10 V CC A11 GEB1/IO110RSB1 A12 GEA0/IO107RSB1 A13 GEC2/IO104RSB1 A14 IO100RSB1 A15 V ...
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Package Pin Assignments 132-Pin QFN Pin Number A3P125 Function C17 IO83RSB1 C18 V B1 CCI C19 TCK C20 VMV1 C21 V PUMP C22 V JTAG C23 V B0 CCI C24 NC C25 NC C26 GCA1/IO55RSB0 C27 GCC0/IO52RSB0 C28 V B0 ...
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QFN Pin Number A3P250 Function A1 GAB2/IO117UPB3 A2 IO117VPB3 CCI A4 GFC1/IO110PDB3 A5 GFB0/IO109NPB3 A6 V CCPLF A7 GFA1/IO108PPB3 A8 GFC2/IO105PPB3 A9 IO103NDB3 A10 V CC A11 GEA1/IO98PPB3 A12 GEA0/IO98NPB3 A13 GEC2/IO95RSB2 A14 IO91RSB2 A15 V ...
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Package Pin Assignments 132-Pin QFN Pin Number A3P250 Function C17 IO74RSB2 C18 V B2 CCI C19 TCK C20 VMV2 C21 V PUMP C22 V JTAG C23 V B1 CCI C24 IO53NSB1 C25 IO51NPB1 C26 GCA1/IO50PPB1 C27 GCC0/IO48NDB1 C28 V B1 ...
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VQFP 100 1 Note: This is the top view of the package. Figure 3-4 • Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. v1.4 ProASIC3 Packaging ...
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Package Pin Assignments 100-Pin VQFP Pin Number A3P030 Function 1 GND 2 IO82RSB1 3 IO81RSB1 4 IO80RSB1 5 IO79RSB1 6 IO78RSB1 7 IO77RSB1 8 IO76RSB1 9 GND 10 IO75RSB1 11 IO74RSB1 12 GEC0/IO73RSB1 13 GEA0/IO72RSB1 14 GEB0/IO71RSB1 15 IO70RSB1 16 ...
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VQFP Pin Number A3P060 Function 1 GND 2 GAA2/IO51RSB1 3 IO52RSB1 4 GAB2/IO53RSB1 5 IO95RSB1 6 GAC2/IO94RSB1 7 IO93RSB1 8 IO92RSB1 9 GND 10 GFB1/IO87RSB1 11 GFB0/IO86RSB1 12 V COMPLF 13 GFA0/IO85RSB1 14 V CCPLF 15 GFA1/IO84RSB1 16 GFA2/IO83RSB1 ...
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Package Pin Assignments 100-Pin VQFP Pin Number A3P125 Function 1 GND 2 GAA2/IO67RSB1 3 IO68RSB1 4 GAB2/IO69RSB1 5 IO132RSB1 6 GAC2/IO131RSB1 7 IO130RSB1 8 IO129RSB1 9 GND 10 GFB1/IO124RSB1 11 GFB0/IO123RSB1 12 V COMPLF 13 GFA0/IO122RSB1 14 V CCPLF 15 ...
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VQFP Pin Number A3P250 Function 1 GND 2 GAA2/IO118UDB3 3 IO118VDB3 4 GAB2/IO117UDB3 5 IO117VDB3 6 GAC2/IO116UDB3 7 IO116VDB3 8 IO112PSB3 9 GND 10 GFB1/IO109PDB3 11 GFB0/IO109NDB3 12 V COMPLF 13 GFA0/IO108NPB3 14 V CCPLF 15 GFA1/IO108PPB3 16 GFA2/IO107PSB3 ...
Page 144
Package Pin Assignments 144-Pin TQFP 144 1 Note: This is the top view of the package. Figure 3-5 • Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx 144-Pin TQFP v1.4 ...
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TQFP Pin Number A3P060 Function 1 GAA2/IO51RSB1 2 IO52RSB1 3 GAB2/IO53RSB1 4 IO95RSB1 5 GAC2/IO94RSB1 6 IO93RSB1 7 IO92RSB1 8 IO91RSB1 GND CCI 12 IO90RSB1 13 GFC1/IO89RSB1 14 GFC0/IO88RSB1 15 GFB1/IO87RSB1 16 ...
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Package Pin Assignments 144-Pin TQFP Pin Number A3P060 Function 109 NC 110 NC 111 GBA1/IO24RSB0 112 GBA0/IO23RSB0 113 GBB1/IO22RSB0 114 GBB0/IO21RSB0 115 GBC1/IO20RSB0 116 GBC0/IO19RSB0 117 V B0 CCI 118 GND 119 V CC 120 IO18RSB0 121 IO17RSB0 122 IO16RSB0 ...
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TQFP Pin Number A3P125 Function 1 GAA2/IO67RSB1 2 IO68RSB1 3 GAB2/IO69RSB1 4 IO132RSB1 5 GAC2/IO131RSB1 6 IO130RSB1 7 IO129RSB1 8 IO128RSB1 GND CCI 12 IO127RSB1 13 GFC1/IO126RSB1 14 GFC0/IO125RSB1 15 GFB1/IO124RSB1 16 ...
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Package Pin Assignments 144-Pin TQFP Pin Number A3P125 Function 109 GBA1/IO40RSB0 110 GBA0/IO39RSB0 111 GBB1/IO38RSB0 112 GBB0/IO37RSB0 113 GBC1/IO36RSB0 114 GBC0/IO35RSB0 115 IO34RSB0 116 IO33RSB0 117 V B0 CCI 118 GND 119 V CC 120 IO29RSB0 121 IO28RSB0 122 IO27RSB0 ...
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PQFP 208 1 Note: This is the top view of the package. Figure 3-6 • Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. 208-Pin PQFP v1.4 ProASIC3 Packaging ...
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Package Pin Assignments 208-Pin PQFP Pin Number A3P125 Function 1 GND 2 GAA2/IO67RSB1 3 IO68RSB1 4 GAB2/IO69RSB1 5 IO132RSB1 6 GAC2/IO131RSB1 IO130RSB1 10 IO129RSB1 IO128RSB1 ...
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PQFP Pin Number A3P125 Function 109 TRST 110 V JTAG 111 GDA0/IO66RSB0 112 GDA1/IO65RSB0 113 GDB0/IO64RSB0 114 GDB1/IO63RSB0 115 GDC0/IO62RSB0 116 GDC1/IO61RSB0 117 NC 118 NC 119 NC 120 NC 121 NC 122 GND 123 V B0 CCI 124 ...
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Package Pin Assignments 208-Pin PQFP Pin Number A3P250 Function 1 GND 2 GAA2/IO118UDB3 3 IO118VDB3 4 GAB2/IO117UDB3 5 IO117VDB3 6 GAC2/IO116UDB3 7 IO116VDB3 8 IO115UDB3 9 IO115VDB3 10 IO114UDB3 11 IO114VDB3 12 IO113PDB3 13 IO113NDB3 14 IO112PDB3 15 IO112NDB3 16 ...
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PQFP Pin Number A3P250 Function 109 TRST 110 V JTAG 111 GDA0/IO60VDB1 112 GDA1/IO60UDB1 113 GDB0/IO59VDB1 114 GDB1/IO59UDB1 115 GDC0/IO58VDB1 116 GDC1/IO58UDB1 117 IO57VDB1 118 IO57UDB1 119 IO56NDB1 120 IO56PDB1 121 IO55RSB1 122 GND 123 V B1 CCI 124 ...
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Package Pin Assignments 208-Pin PQFP Pin Number A3P400 Function 1 GND 2 GAA2/IO155UDB3 3 IO155VDB3 4 GAB2/IO154UDB3 5 IO154VDB3 6 GAC2/IO153UDB3 7 IO153VDB3 8 IO152UDB3 9 IO152VDB3 10 IO151UDB3 11 IO151VDB3 12 IO150PDB3 13 IO150NDB3 14 IO149PDB3 15 IO149NDB3 16 ...
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PQFP Pin Number A3P400 Function 109 TRST 110 V JTAG 111 GDA0/IO79VDB1 112 GDA1/IO79UDB1 113 GDB0/IO78VDB1 114 GDB1/IO78UDB1 115 GDC0/IO77VDB1 116 GDC1/IO77UDB1 117 IO76VDB1 118 IO76UDB1 119 IO75NDB1 120 IO75PDB1 121 IO74RSB1 122 GND 123 V B1 CCI 124 ...
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Package Pin Assignments 208-Pin PQFP Pin Number A3P600 Function 1 GND 2 GAA2/IO174PDB3 3 IO174NDB3 4 GAB2/IO173PDB3 5 IO173NDB3 6 GAC2/IO172PDB3 7 IO172NDB3 8 IO171PDB3 9 IO171NDB3 10 IO170PDB3 11 IO170NDB3 12 IO169PDB3 13 IO169NDB3 14 IO168PDB3 15 IO168NDB3 16 ...
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PQFP Pin Number A3P600 Function 109 TRST 110 V JTAG 111 GDA0/IO88NDB1 112 GDA1/IO88PDB1 113 GDB0/IO87NDB1 114 GDB1/IO87PDB1 115 GDC0/IO86NDB1 116 GDC1/IO86PDB1 117 IO84NDB1 118 IO84PDB1 119 IO82NDB1 120 IO82PDB1 121 IO81PSB1 122 GND 123 V B1 CCI 124 ...
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Package Pin Assignments 208-Pin PQFP Pin Number A3P1000 Function 1 GND 2 GAA2/IO225PDB3 3 IO225NDB3 4 GAB2/IO224PDB3 5 IO224NDB3 6 GAC2/IO223PDB3 7 IO223NDB3 8 IO222PDB3 9 IO222NDB3 10 IO220PDB3 11 IO220NDB3 12 IO218PDB3 13 IO218NDB3 14 IO216PDB3 15 IO216NDB3 16 ...
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PQFP Pin Number A3P1000 Function 109 TRST 110 V JTAG 111 GDA0/IO113NDB1 112 GDA1/IO113PDB1 113 GDB0/IO112NDB1 114 GDB1/IO112PDB1 115 GDC0/IO111NDB1 116 GDC1/IO111PDB1 117 IO109NDB1 118 IO109PDB1 119 IO106NDB1 120 IO106PDB1 121 IO104PSB1 122 GND 123 V B1 CCI 124 ...
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Package Pin Assignments 144-Pin FBGA 12 11 Note: This is the bottom view of the package. Figure 3-7 • Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner 10 ...
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FBGA Pin Number A3P060 Function A1 GNDQ A2 VMV0 A3 GAB0/IO04RSB0 A4 GAB1/IO05RSB0 A5 IO08RSB0 A6 GND A7 IO11RSB0 IO16RSB0 A10 GBA0/IO23RSB0 A11 GBA1/IO24RSB0 A12 GNDQ B1 GAB2/IO53RSB1 B2 GND B3 GAA0/IO02RSB0 B4 GAA1/IO03RSB0 B5 ...
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Package Pin Assignments 144-Pin FBGA Pin Number A3P060 Function K1 GEB0/IO74RSB1 K2 GEA1/IO73RSB1 K3 GEA0/IO72RSB1 K4 GEA2/IO71RSB1 K5 IO65RSB1 K6 IO64RSB1 K7 GND K8 IO57RSB1 K9 GDC2/IO56RSB1 K10 GND K11 GDA0/IO50RSB0 K12 GDB0/IO48RSB0 L1 GND L2 VMV1 L3 GEB2/IO70RSB1 L4 ...
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FBGA Pin Number A3P125 Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO11RSB0 A6 GND A7 IO18RSB0 IO25RSB0 A10 GBA0/IO39RSB0 A11 GBA1/IO40RSB0 A12 GNDQ B1 GAB2/IO69RSB1 B2 GND B3 GAA0/IO00RSB0 B4 GAA1/IO01RSB0 B5 ...
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Package Pin Assignments 144-Pin FBGA Pin Number A3P125 Function K1 GEB0/IO109RSB1 K2 GEA1/IO108RSB1 K3 GEA0/IO107RSB1 K4 GEA2/IO106RSB1 K5 IO100RSB1 K6 IO98RSB1 K7 GND K8 IO73RSB1 K9 GDC2/IO72RSB1 K10 GND K11 GDA0/IO66RSB0 K12 GDB0/IO64RSB0 L1 GND L2 VMV1 L3 GEB2/IO105RSB1 L4 ...
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FBGA Pin Number A3P250 Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO16RSB0 A6 GND A7 IO29RSB0 IO33RSB0 A10 GBA0/IO39RSB0 A11 GBA1/IO40RSB0 A12 GNDQ B1 GAB2/IO117UDB3 B2 GND B3 GAA0/IO00RSB0 B4 GAA1/IO01RSB0 B5 ...
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Package Pin Assignments 144-Pin FBGA Pin Number A3P250 Function K1 GEB0/IO99NDB3 K2 GEA1/IO98PDB3 K3 GEA0/IO98NDB3 K4 GEA2/IO97RSB2 K5 IO90RSB2 K6 IO84RSB2 K7 GND K8 IO66RSB2 K9 GDC2/IO63RSB2 K10 GND K11 GDA0/IO60VDB1 K12 GDB0/IO59VDB1 L1 GND L2 VMV3 L3 GEB2/IO96RSB2 L4 ...
Page 167
FBGA Pin Number A3P400 Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO16RSB0 A6 GND A7 IO30RSB0 IO34RSB0 A10 GBA0/IO58RSB0 A11 GBA1/IO59RSB0 A12 GNDQ B1 GAB2/IO154UDB3 B2 GND B3 GAA0/IO00RSB0 B4 GAA1/IO01RSB0 B5 ...
Page 168
Package Pin Assignments 144-Pin FBGA Pin Number A3P400 Function K1 GEB0/IO136NDB3 K2 GEA1/IO135PDB3 K3 GEA0/IO135NDB3 K4 GEA2/IO134RSB2 K5 IO127RSB2 K6 IO121RSB2 K7 GND K8 IO104RSB2 K9 GDC2/IO82RSB2 K10 GND K11 GDA0/IO79VDB1 K12 GDB0/IO78VDB1 L1 GND L2 VMV3 L3 GEB2/IO133RSB2 L4 ...
Page 169
FBGA Pin Number A3P600 Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO10RSB0 A6 GND A7 IO34RSB0 IO50RSB0 A10 GBA0/IO58RSB0 A11 GBA1/IO59RSB0 A12 GNDQ B1 GAB2/IO173PDB3 B2 GND B3 GAA0/IO00RSB0 B4 GAA1/IO01RSB0 B5 ...
Page 170
Package Pin Assignments 144-Pin FBGA Pin Number A3P600 Function K1 GEB0/IO145NDB3 K2 GEA1/IO144PDB3 K3 GEA0/IO144NDB3 K4 GEA2/IO143RSB2 K5 IO119RSB2 K6 IO111RSB2 K7 GND K8 IO94RSB2 K9 GDC2/IO91RSB2 K10 GND K11 GDA0/IO88NDB1 K12 GDB0/IO87NDB1 L1 GND L2 VMV3 L3 GEB2/IO142RSB2 L4 ...
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FBGA Pin Number A3P1000 Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO10RSB0 A6 GND A7 IO44RSB0 IO69RSB0 A10 GBA0/IO76RSB0 A11 GBA1/IO77RSB0 A12 GNDQ B1 GAB2/IO224PDB3 B2 GND B3 GAA0/IO00RSB0 B4 GAA1/IO01RSB0 B5 ...
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Package Pin Assignments 144-Pin FBGA Pin Number A3P1000 Function K1 GEB0/IO189NDB3 K2 GEA1/IO188PDB3 K3 GEA0/IO188NDB3 K4 GEA2/IO187RSB2 K5 IO169RSB2 K6 IO152RSB2 K7 GND K8 IO117RSB2 K9 GDC2/IO116RSB2 K10 GND K11 GDA0/IO113NDB1 K12 GDB0/IO112NDB1 L1 GND L2 VMV3 L3 GEB2/IO186RSB2 L4 ...
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FBGA Note: This is the bottom view of the package. Figure 3-8 • Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner ...
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Package Pin Assignments 256-Pin FBGA Pin Number A3P250 Function A1 GND A2 GAA0/IO00RSB0 A3 GAA1/IO01RSB0 A4 GAB0/IO02RSB0 A5 IO07RSB0 A6 IO10RSB0 A7 IO11RSB0 A8 IO15RSB0 A9 IO20RSB0 A10 IO25RSB0 A11 IO29RSB0 A12 IO33RSB0 A13 GBB1/IO38RSB0 A14 GBA0/IO39RSB0 A15 GBA1/IO40RSB0 A16 ...
Page 175
FBGA Pin Number A3P250 Function G13 GCC1/IO48PPB1 G14 IO47NPB1 G15 IO54PDB1 G16 IO54NDB1 H1 GFB0/IO109NPB3 H2 GFA0/IO108NDB3 H3 GFB1/IO109PPB3 H4 V COMPLF H5 GFC0/IO110NPB3 GND H8 GND H9 GND H10 GND H11 V CC H12 ...
Page 176
Package Pin Assignments 256-Pin FBGA Pin Number A3P250 Function P9 IO76RSB2 P10 IO71RSB2 P11 IO66RSB2 P12 NC P13 TCK P14 V PUMP P15 TRST P16 GDA0/IO60VDB1 R1 GEA1/IO98PDB3 R2 GEA0/IO98NDB3 GEC2/IO95RSB2 R5 IO91RSB2 R6 IO88RSB2 R7 IO84RSB2 ...
Page 177
FBGA Pin Number A3P400 Function A1 GND A2 GAA0/IO00RSB0 A3 GAA1/IO01RSB0 A4 GAB0/IO02RSB0 A5 IO16RSB0 A6 IO17RSB0 A7 IO22RSB0 A8 IO28RSB0 A9 IO34RSB0 A10 IO37RSB0 A11 IO41RSB0 A12 IO43RSB0 A13 GBB1/IO57RSB0 A14 GBA0/IO58RSB0 A15 GBA1/IO59RSB0 A16 GND B1 GAB2/IO154UDB3 ...
Page 178
Package Pin Assignments 256-Pin FBGA Pin Number A3P400 Function G13 GCC1/IO67PPB1 G14 IO64NPB1 G15 IO73PDB1 G16 IO73NDB1 H1 GFB0/IO146NPB3 H2 GFA0/IO145NDB3 H3 GFB1/IO146PPB3 H4 V COMPLF H5 GFC0/IO147NPB3 GND H8 GND H9 GND H10 GND H11 ...
Page 179
FBGA Pin Number A3P400 Function P9 IO98RSB2 P10 IO95RSB2 P11 IO88RSB2 P12 IO84RSB2 P13 TCK P14 V PUMP P15 TRST P16 GDA0/IO79VDB1 R1 GEA1/IO135PDB3 R2 GEA0/IO135NDB3 R3 IO127RSB2 R4 GEC2/IO132RSB2 R5 IO123RSB2 R6 IO118RSB2 R7 IO112RSB2 R8 IO106RSB2 R9 ...
Page 180
Package Pin Assignments 256-Pin FBGA Pin Number A3P600 Function A1 GND A2 GAA0/IO00RSB0 A3 GAA1/IO01RSB0 A4 GAB0/IO02RSB0 A5 IO11RSB0 A6 IO16RSB0 A7 IO18RSB0 A8 IO28RSB0 A9 IO34RSB0 A10 IO37RSB0 A11 IO41RSB0 A12 IO43RSB0 A13 GBB1/IO57RSB0 A14 GBA0/IO58RSB0 A15 GBA1/IO59RSB0 A16 ...
Page 181
FBGA Pin Number A3P600 Function G13 GCC1/IO69PPB1 G14 IO65NPB1 G15 IO75PDB1 G16 IO75NDB1 H1 GFB0/IO163NPB3 H2 GFA0/IO162NDB3 H3 GFB1/IO163PPB3 H4 V COMPLF H5 GFC0/IO164NPB3 GND H8 GND H9 GND H10 GND H11 V CC H12 ...
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Package Pin Assignments 256-Pin FBGA Pin Number A3P600 Function P9 IO107RSB2 P10 IO104RSB2 P11 IO97RSB2 P12 VMV1 P13 TCK P14 V PUMP P15 TRST P16 GDA0/IO88NDB1 R1 GEA1/IO144PDB3 R2 GEA0/IO144NDB3 R3 IO139RSB2 R4 GEC2/IO141RSB2 R5 IO132RSB2 R6 IO127RSB2 R7 IO121RSB2 ...
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FBGA Pin Number A3P1000 Function A1 GND A2 GAA0/IO00RSB0 A3 GAA1/IO01RSB0 A4 GAB0/IO02RSB0 A5 IO16RSB0 A6 IO22RSB0 A7 IO28RSB0 A8 IO35RSB0 A9 IO45RSB0 A10 IO50RSB0 A11 IO55RSB0 A12 IO61RSB0 A13 GBB1/IO75RSB0 A14 GBA0/IO76RSB0 A15 GBA1/IO77RSB0 A16 GND B1 GAB2/IO224PDB3 ...
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Package Pin Assignments 256-Pin FBGA Pin Number A3P1000 Function H3 GFB1/IO208PPB3 H4 V COMPLF H5 GFC0/IO209NPB3 GND H8 GND H9 GND H10 GND H11 V CC H12 GCC0/IO91NPB1 H13 GCB1/IO92PPB1 H14 GCA0/IO93NPB1 H15 IO96NPB1 H16 GCB0/IO92NPB1 ...
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FBGA Pin Number A3P1000 Function R5 IO168RSB2 R6 IO163RSB2 R7 IO157RSB2 R8 IO149RSB2 R9 IO143RSB2 R10 IO138RSB2 R11 IO131RSB2 R12 IO125RSB2 R13 GDB2/IO115RSB2 R14 TDI R15 GNDQ R16 TDO T1 GND T2 IO183RSB2 T3 GEB2/IO186RSB2 T4 IO172RSB2 T5 IO170RSB2 ...
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Package Pin Assignments 484-Pin FBGA Note: This is the bottom view of the package. Figure 3-9 • Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx ...
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FBGA Pin Number A3P400 Function A1 GND A2 GND CCI IO15RSB0 A7 IO18RSB0 A10 IO23RSB0 A11 IO29RSB0 A12 IO35RSB0 A13 IO36RSB0 A14 NC A15 NC A16 IO50RSB0 ...
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Package Pin Assignments 484-Pin FBGA Pin Number A3P400 Function E21 NC E22 IO154VDB3 F5 IO155VDB3 F6 IO11RSB0 F7 IO07RSB0 F8 GAC0/IO04RSB0 F9 GAC1/IO05RSB0 F10 IO20RSB0 F11 IO24RSB0 F12 IO33RSB0 F13 IO39RSB0 F14 ...
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FBGA Pin Number A3P400 Function K19 IO73NDB1 K20 NC K21 NC K22 GFB0/IO146NPB3 L5 GFA0/IO145NDB3 L6 GFB1/IO146PPB3 L7 V COMPLF L8 GFC0/IO147NPB3 L10 GND L11 GND L12 GND ...
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Package Pin Assignments 484-Pin FBGA Pin Number A3P400 Function R17 GDB1/IO78UPB1 R18 GDC1/IO77UDB1 R19 IO75NDB1 R20 V CC R21 NC R22 IO140NDB3 T5 IO138PPB3 T6 GEC1/IO137PPB3 T7 IO131RSB2 T8 GNDQ T9 GEA2/IO134RSB2 ...
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FBGA Pin Number A3P400 Function Y15 V CC Y16 NC Y17 NC Y18 GND Y19 NC Y20 NC Y21 NC Y22 V B1 CCI AA1 GND AA2 V B3 CCI AA3 NC AA4 NC AA5 NC AA6 NC AA7 ...
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Package Pin Assignments 484-Pin FBGA Pin Number A3P600 Function A1 GND A2 GND A3 VCCIB0 IO09RSB0 A7 IO15RSB0 A10 IO22RSB0 A11 IO23RSB0 A12 IO29RSB0 A13 IO35RSB0 A14 NC A15 NC A16 ...
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FBGA Pin Number A3P600 Function E21 NC E22 IO173NDB3 F5 IO174NDB3 F6 VMV3 F7 IO07RSB0 F8 GAC0/IO04RSB0 F9 GAC1/IO05RSB0 F10 IO20RSB0 F11 IO24RSB0 F12 IO33RSB0 F13 IO39RSB0 F14 IO44RSB0 F15 GBC0/IO54RSB0 ...
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Package Pin Assignments 484-Pin FBGA Pin Number A3P600 Function K19 IO75NDB1 K20 NC K21 IO76NDB1 K22 IO76PDB1 IO155PDB3 GFB0/IO163NPB3 L5 GFA0/IO162NDB3 L6 GFB1/IO163PPB3 L7 V COMPLF L8 GFC0/IO164NPB3 L10 GND L11 ...
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FBGA Pin Number A3P600 Function R17 GDB1/IO87PPB1 R18 GDC1/IO86PDB1 R19 IO84NDB1 R20 V CC R21 IO81NDB1 R22 IO82PDB1 T1 IO152PDB3 T2 IO152NDB3 IO150NDB3 T5 IO147PPB3 T6 GEC1/IO146PPB3 T7 IO140RSB2 T8 GNDQ T9 GEA2/IO143RSB2 T10 IO126RSB2 T11 ...
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Package Pin Assignments 484-Pin FBGA Pin Number A3P600 Function Y15 V CC Y16 NC Y17 NC Y18 GND Y19 NC Y20 NC Y21 NC Y22 V B1 CCI AA1 GND AA2 V B3 CCI AA3 NC AA4 NC AA5 NC ...
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FBGA Pin Number A3P1000 Function A1 GND A2 GND CCI A4 IO07RSB0 A5 IO09RSB0 A6 IO13RSB0 A7 IO18RSB0 A8 IO20RSB0 A9 IO26RSB0 A10 IO32RSB0 A11 IO40RSB0 A12 IO41RSB0 A13 IO53RSB0 A14 IO59RSB0 A15 IO64RSB0 A16 IO65RSB0 ...
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FBGA Pin Number A3P1000 Function E21 NC E22 IO84PDB1 IO215PDB3 F3 IO215NDB3 F4 IO224NDB3 F5 IO225NDB3 F6 VMV3 F7 IO11RSB0 F8 GAC0/IO04RSB0 F9 GAC1/IO05RSB0 F10 IO25RSB0 F11 IO36RSB0 F12 IO42RSB0 F13 IO49RSB0 F14 IO56RSB0 F15 GBC0/IO72RSB0 ...
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FBGA Pin Number A3P1000 Function K19 IO88NDB1 K20 IO94NPB1 K21 IO98NDB1 K22 IO98PDB1 IO200PDB3 L3 IO210NPB3 L4 GFB0/IO208NPB3 L5 GFA0/IO207NDB3 L6 GFB1/IO208PPB3 L7 V COMPLF L8 GFC0/IO209NPB3 L10 GND L11 GND L12 GND ...
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FBGA Pin Number A3P1000 Function R17 GDB1/IO112PPB1 R18 GDC1/IO111PDB1 R19 IO107NDB1 R20 V CC R21 IO104NDB1 R22 IO105PDB1 T1 IO198PDB3 T2 IO198NDB3 IO194PPB3 T5 IO192PPB3 T6 GEC1/IO190PPB3 T7 IO192NPB3 T8 GNDQ T9 GEA2/IO187RSB2 T10 IO161RSB2 T11 ...