A3P015-1FG144 ACTEL [Actel Corporation], A3P015-1FG144 Datasheet - Page 91

• Manufacturer Part Number: A3P015-1FG144
• Description: ProASIC3 Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Figure 2-26 • Timing Model and Waveforms
Table 2-97 • Register Delays
CLK
Data
EN
Out
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
PRE
CLR
CLKQ
SUD
HD
SUE
HE
CLR2Q
PRE2Q
REMCLR
RECCLR
REMPRE
RECPRE
WCLR
WPRE
CKMPWH
CKMPWL
For specific junction temperature and voltage supply levels, refer to
values.
Timing Characteristics
Clock-to-Q of the Core Register
Data Setup Time for the Core Register
Data Hold Time for the Core Register
Enable Setup Time for the Core Register
Enable Hold Time for the Core Register
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width HIGH for the Core Register
Clock Minimum Pulse Width LOW for the Core Register
Commercial-Case Conditions: T
50%
50%
t
SUE
t
HE
50%
t
CLKQ
50%
t
SUD
0
t
HD
Description
t
50%
PRE2Q
50%
J
50%
t
= 70°C, Worst-Case V
WPRE
50%
50%
50%
v1.3
t
t
RECPRE
WCLR
50%
t
50%
50%
CLR2Q
CC
50%
= 1.425 V
t
RECCLR
ProASIC3 DC and Switching Characteristics
Table 2-6 on page 2-6
50%
0.55 0.63 0.74 0.89
0.43 0.49 0.57 0.69
0.00 0.00 0.00 0.00
0.45 0.52 0.61 0.73
0.00 0.00 0.00 0.00
0.40 0.45 0.53 0.64
0.40 0.45 0.53 0.64
0.00 0.00 0.00 0.00
0.22 0.25 0.30 0.36
0.00 0.00 0.00 0.00
0.22 0.25 0.30 0.36
0.22 0.25 0.30 0.36
0.22 0.25 0.30 0.36
0.32 0.37 0.43 0.52
0.36 0.41 0.48 0.57
–2
t
CKMPWH
t
50%
REMPRE
–1
t
50%
CKMPWL
Std.
for derating
–F
50%
50%
t
REMCLR
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2 - 77