ADUM6132_08 AD [Analog Devices], ADUM6132_08 Datasheet - Page 10

• Manufacturer Part Number: ADUM6132_08
• Description: Isolated Half-Bridge Gate Driver with Integrated Isolated High-Side Supply
• Manufacturer: AD [Analog Devices]

ADuM6132
TERMINOLOGY
Channel-to-Channel Matching
Channel-to-channel matching with rising or falling matching
edge polarity is the magnitude of the propagation delay differ-
ence between two channels of the same part when the inputs
are both rising edges or both falling edges. The loads on each
channel are equal.
Channel-to-channel matching with rising vs. falling opposite
edge polarity is the magnitude of the propagation delay differ-
ence between two channels of the same part when one input is
a rising edge and one input is a falling edge. The loads on each
channel are equal.
Maximum Output Current
The maximum output current is the maximum isolated supply
current that the ADuM6132 can provide. This current supports
external loads as well as the needs of the ADuM6132 Channel A
output circuitry. This is achieved via external connection of the
V
(see Figure 16). The net current available to power external loads
is the ADuM6132 output current, I
supply current, I
Maximum Switching Frequency
The maximum switching frequency is the maximum signal
frequency at which the specified timing parameters are guar-
anteed. Operation beyond the maximum switching frequency
is not recommended, because high switching rates can cause
droop in the output supply voltage.
ISO
pin to the V
DDA
DDA
.
pin and of the GND
ISO
, minus the Channel A
ISO
pin to the GND
A
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pin
Minimum Pulse Width
The minimum pulse width is the shortest pulse width at which
the specified pulse width distortion is guaranteed. Operation
below the minimum pulse width is not recommended.
Part-to-Part Matching
Part-to-part matching is the magnitude of the propagation
delay difference between the same channels of two different
parts. This includes rising vs. rising edges, falling vs. falling
edges, or rising vs. falling edges. The supply voltages, temp-
eratures, and loads of each part are equal.
Propagation Delay
The propagation delay is the time that it takes a logic signal to
propagate through a component. The propagation delay to a
logic low output may differ from the propagation delay to a
logic high output.
The t
of the falling edge of the V
the falling edge of the V
delay is measured from the 50% level of the rising edge of the
V
or V
Capacitive Load (C
The output capacitive load simulates a typical FET, IGBT, or
buffer for timing or current measurements. This load includes
all discrete and parasitic capacitive loads on the output.
IA
or V
OB
PHL
signal.
IB
propagation delay is measured from the 50% level
signal to the 50% level of the rising edge of the V
L
)
OA
IA
or V
or V
OB
IB
signal. The t
signal to the 50% level of
PLH
propagation
OA