HT82A520R HOLTEK [Holtek Semiconductor Inc], HT82A520R Datasheet - Page 48

• Manufacturer Part Number: HT82A520R
• Description: Full Speed USB 8-Bit OTP MCU with SPI
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

The SIES register is only used for EP0 except for the NMI bit, which can control all endpoints
The MISC register combines command and status to control the desired endpoint FIFO action and to show the status of
the desired endpoint FIFO. MISC will be cleared by a USB reset signal.
Rev.1.00
Bit No.
Bit No.
3~4
0
1
2
3
4
5
6
7
0
1
2
5
6
7
NO ACK
REQUEST
SETCMD
CRCF
Label
ASET
READY
CLEAR
ERR
OUT
NMI
Label
LEN0
IN
TX
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R
R
This bit is used to configure the SIE to automatically change the device address by the
value stored in the AWR register. When this bit is set to 1 by firmware, the SIE will up-
date the device address by the value stored in the AWR register after the PC host has
successfully read the data from he device by an IN operation. Otherwise, when this bit
is cleared to 0 , the SIE will update the device address immediately after an address is
written to the AWR register. So, in order to work properly, the firmware has to clear this
bit after a next valid SETUP token is received. Default value is 0 .
This bit is used to indicate that some errors have occurred when the FIFO is accessed.
This bit is set by SIE and should be cleared by firmware. This bit is used for all endpoint.
Default value is 0 .
This bit is used to indicate the OUT token (except the OUT zero length token) has been
received. The firmware clears this bit after the OUT data has been read. Also, this bit
will be cleared by SIE after the next valid SETUP token is received. Default value is 0 .
This bit is used to indicate the current USB receiving signal from PC host is IN token.
This bit will set to 1 once SIE discover ther are some error condition so the SIE is not
response (NAK or ACK or DATA) for the USB token. This bit is set by SIE and clear by
F/W.
Unused bit, read as 0
This bit will set to 1 when there are the following three condition is happened: CRC er-
ror, PID error, Bit stuffing error.
This bit is set by SIE and clear by F/W. Default value is 0 .
NAK token interrupt mask flag. If this bit set, when the device sent a NAK token to the
host, an interrupt will be disabled. Otherwise if this bit is cleared, when the device
sends a NAK token to the host, it will enter the interrupt sub-routine. This bit is used for
all endpoint. Default value is 0 .
After setting the status of the desired one, FIFO can be requested by setting this bit
high. After finishing, this bit must be set low. Default value is 0 .
To represent the direction and transition end MCU access. When set to logic 1, the
MCU desires to write data to the FIFO. After finishing, this bit must be set to logic 0
before terminating request to represent transition end. For an MCU read operation,
this bit must be set to logic 0 and set to logic 1 after finishing. Default value is 0 .
MCU requests to clear the FIFO, even if the FIFO is not ready. After clearing the
FIFO, the USB interface will send force_tx_err to tell the Host that data under-run if
the Host wants to read data. Default value is 0 .
Unused bit, read as 0
To show that the data in the FIFO is a setup command. This bit is set by Hardware
and clear by Firmware. Default value is 0 .
To show that the desired FIFO is ready.
To show that the host sent a 0-sized packet to the MCU. This bit must be cleared by a
read action to the corresponding FIFO.
MISC Register
SIES Register
48
Function
Function
HT82A520R/HT82A620R
October 23, 2009