HT82J97A_08 HOLTEK [Holtek Semiconductor Inc], HT82J97A_08 Datasheet - Page 25

• Manufacturer Part Number: HT82J97A_08
• Description: USB Joystick Encoder 8-Bit MCU
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

ADC High-byte Data Register ADCR (Address 0X1E)
Table High Byte Pointer for Current Table Read TBHP (Address 0X1F)
PWM Base Period Register PWMBR (Address 0X18)
This register is used to define the base period of the PWM cycle period. The period is defined according to the following
equation:
Base period = (4/f
Where 4/f
Where PWMBR = 1~255, PWMBR=0 is not available
PWM cycle period = 256 Base period
Base period equals to 1/256 duty cycle.
PWM Duty Register PWM1DR (Address 0XCH) and PWM2DR (Address 0XDH)
This register is used to define the duty of the PWM1 output (PC2) or PWM2 output (PC3) respectively. Both PWM cycle
frequency is defined according to the following equation:
PWM1 duty = (PWM1DR+1)/PWM cycle 100% period
Where PWM1DR= 0~255
If the PWM function is enabled by setting the corresponding bit (PWM1_EN or PWM2_EN of Port C), the PWM output
(PC2 or PC3) pins always output the PWM signal whether the corresponding control register bit (PCC2 or PCC3 ) is de-
fined as in input or output mode.
OTP Options
The LVR voltage is define as 2.7V 0.3V and default is enable.
Rev. 1.60
Register Bits
Register Bits
Register Bits
PWM1DR (0XCH)
PWM2DR (0XDH)
PWMBR
(0X1E)
(0X1F)
(0X18)
ADCR
No.
TBHP
10
1
2
3
4
5
6
7
8
9
Register
WDT clock source: RC (system/4) (default: T1)
WDT clock source: enable/disable for normal mode (default: disable)
PA0~PA7 ,PB4, PB7 wake-up by bit (PA2, PA3 both wake-up by falling or rising edge) (default: non wake-up)
PA0~PA7 pull-high by bit (default: Pull-high)
PC0~3,PB pull-high by nibble (default: Pull-high)
2.7 V (error 0.3V) LVR enable/disable (default: enable)
PA0~PA3, PB2, PB3 Pull-low by bit (default: non pull-low 30k )
TBHP enable/disable (default: disable)
PA output mode (CMOS/NMOS/PMOS) by bit (default: CMOS)
SYS
CLR WDT , 1 or 2 instructions
7~0
2~0
7~0
or 1/f
SYS
PGC2~PG0
SYS
PG7~PG0
PD7~PD0
Labels
Labels
Labels
) (PWMBR+1) or (1/f
is defined by PWM_S bit of PORT_PC
Bits
7~0
Read/Write
Read/Write
Read/Write
Read/Write
R/W
R
R
R
SYS
)
ADCDR
Option
Option
Option
Option
(PWMBR+1)
25
Option
The ADCDR stores the result of a valid ADC conversion
bit7~bit0.
Store current table read bit10~bit8 data
Used to define the base period of the PWM
Range =2~256 Base Period
Where PWMBR=1~255, PWMBR=0 is not available
Used to define the PWM duty
HT82J97E/HT82J97A
Functions
Functions
Functions
Functions
December 23, 2008