ISPLSI2032VE180LB49 LATTICE [Lattice Semiconductor], ISPLSI2032VE180LB49 Datasheet
ISPLSI2032VE180LB49
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ISPLSI2032VE180LB49 Summary of contents
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Features • SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 1000 PLD Gates — 32 I/O Pins, Two Dedicated Inputs — 32 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — ...
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Functional Block Diagram Figure 1. ispLSI 2032VE Functional Block Diagram GOE 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 ...
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Absolute Maximum Ratings Supply Voltage V .................................. -0.5 to +5.4V cc Input Voltage Applied ............................... -0.5 to +5.6V Off-State Output Voltage Applied ............ -0.5 to +5.6V Storage Temperature .............................. -65 to +150°C Case Temp. with Power Applied .............. -55 to ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see Figure 2) TEST ...
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External Timing Parameters 3 TEST PARAMETER # COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay pd2 f max A 3 Clock Frequency with Internal Feedback f – 4 Clock Frequency ...
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External Timing Parameters 3 TEST PARAMETER # COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay pd2 f max A 3 Clock Frequency with Internal Feedback f – 4 Clock Frequency ...
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Internal Timing Parameters 2 PARAMETER # Inputs t 20 Input Buffer Delay Dedicated Input Delay din GRP t 22 GRP Delay grp GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc Product ...
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Internal Timing Parameters 2 PARAMETER # Inputs t 20 Input Buffer Delay Dedicated Input Delay din GRP t grp 22 GRP Delay GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc t 4ptbpr 24 4 ...
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Timing Model I/O Cell Ded. In #21 I/O Delay I/O Pin #20 (Input) #45 Reset Y0,1,2 GOE Derivations of su, h and co from the Product Term Clock Logic + Reg ...
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Power Consumption Power consumption in the ispLSI 2032VE device de- pends on two primary factors: the speed at which the device is operating and the number of product terms Figure 3. Typical Device Power Consumption vs fmax 150 125 100 ...
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Signal Descriptions Signal Name GOE 0 Global Output Enable input pin Y0 Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs in the device. RESET/Y1 This pin performs two functions: (1) ...
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Pin Configuration ispLSI 2032VE 44-Pin TQFP Pinout Diagram (0.8mm Lead Pitch/10.0 x 10.0mm Body Size) I/O 28 I/O 29 I VCC BSCAN TDI/IN 0 I/O 0 I pins are not to ...
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Pin Configuration ispLSI 2032VE 48-Pin TQFP Pinout Diagram (0.5mm Lead Pitch/7.0 x 7.0mm Body Size) I/O 28 I/O 29 I/O 30 I/O 31 VCC BSCAN 1 TDI/IN 0 I/O 0 I Pins have dual ...
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Part Number Description ispLSI 2032VE – XXX Device Family Device Number 2032VE Speed f 300 = 300 MHz max f 225 = 225 MHz max f 180 = 180 MHz max f 135 = 135 MHz max f 110 = ...
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Ordering Information (Cont.) Lead-Free Packaging FAMILY fmax (MHz) tpd (ns) 300 300 180 180 ispLSI 135 135 110 110 FAMILY fmax (MHz) tpd (ns) ispLSI 180 Revision History Date Version — 10 August 2006 11 Specifications ispLSI 2032VE ...