ISPLSI3192 LATTICE [Lattice Semiconductor], ISPLSI3192 Datasheet

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ISPLSI3192

Manufacturer Part Number
ISPLSI3192
Description
High Density Programmable Logic
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet

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• HIGH-DENSITY PROGRAMMABLE LOGIC
• HIGH PERFORMANCE E
• IN-SYSTEM PROGRAMMABLE
• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE
• OFFERS THE EASE OF USE AND FAST SYSTEM
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
3192_08
Features
— 192 I/O Pins
— 9000 PLD Gates
— 384 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
— Small Logic Block Size for Random Logic
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
— Supports ISP™ or ispJTAG™ Programming
— Increased Manufacturing Yields, Reduced Time-to-
— Reprogram Soldered Devices for Faster Debugging
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
— Five Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to Mini-
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
— PC and UNIX Platforms
Market, and Improved Product Quality
Machines, Address Decoders, etc.
f
t
Logic and Structured Designs
mize Switching Noise
Interconnectivity
Tools, Timing Simulator and ispANALYZER™
max = 100 MHz Maximum Operating Frequency
pd = 10 ns Propagation Delay
2
CMOS
®
TECHNOLOGY
1
The ispLSI 3192 is a High Density Programmable Logic
Device containing 384 Registers, 192 Universal I/O pins,
five Dedicated Clock Input Pins, twelve Output Routing
Pools (ORP), and a Global Routing Pool (GRP) which
allows complete inter-connectivity between all of these
elements. The ispLSI 3192 features 5-Volt in-system
programmability and in-system diagnostic capabilities.
The ispLSI 3192 offers non-volatile reprogrammability of
the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 3192 device is the
Twin Generic Logic Block (Twin GLB) labelled A0, A1...F3.
There are a total of 24 of these Twin GLBs in the ispLSI
3192 device. Each Twin GLB has 24 inputs, a program-
mable AND array and two OR/Exclusive-OR Arrays, and
eight outputs which can be configured to be either com-
binatorial or registered. All Twin GLB inputs come from
the GRP.
Functional Block Diagram
Description
A0
A3
A1
A2
F3
B0
High Density Programmable Logic
ORP
ORP
F2
B1
F1
B2
ORP
ORP
Global Routing Pool
F0
B3
ispLSI
Array
Array
OR
OR
E3
C0
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
ORP
ORP
E2
C1
Twin
GLB
E1
C2
®
ORP
ORP
3192
E0
C3
June 2002
Boundary
D3
D2
D1
D0
0139/3192
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ISPLSI3192 Summary of contents

Page 1

Features • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random ...

Page 2

Functional Block Diagram Figure 1. ispLSI 3192 Functional Block Diagram Generic TOE Logic Output Routing Pool Blocks F3 I/O 1 I/O 0 I I/O 5 I/O 4 I/O 7 I/O 6 I/O 9 I/O 8 I/O ...

Page 3

Description (Continued) All local logic block outputs are brought back into the GRP so they can be connected to the inputs of any other logic block on the device. The device also has 192 I/O cells, each of which is ...

Page 4

Absolute Maximum Ratings Supply Voltage V .................................. -0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to ...

Page 5

Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load conditions (See figure 2) TEST CONDITION A Active ...

Page 6

External Switching Characteristics ...

Page 7

Internal Timing Parameters ...

Page 8

Internal Timing Parameters # ...

Page 9

Timing Model I/O Cell I/O Reg Bypass I/O Pin #24 (Input) Input Register Q D RST #52 # Reset Y3,4 #51 Y0,1,2 GOE0,1 TOE Derivations of su, h and co from the Product ...

Page 10

Power Consumption Power Consumption in the ispLSI 3192 device depends on two primary factors: the speed at which the device is Figure 3. Typical Device Power Consumption vs fmax 640 540 440 340 240 I CC can be estimated for ...

Page 11

Pin Description NAME PQFP PIN NUMBERS I I/O 5 36, 37, 38, I I/O 11 43, 44, 45, I I/O 17 50, 51, 52, I I/O 23 57, 58, 59, I/O 24 ...

Page 12

Signal Locations and Descriptions NAME BGA BALL NUMBERS I I/O 5 M4, N1, N2, P3, R2, T1, I I I/O 17 T3, U2, V1, I I/O 23 V3, W2, Y1, ...

Page 13

Pin Configuration ispLSI 3192 240-pin PQFP 1 I/O 169 2 I/O 170 3 I/O 171 4 I/O 172 5 I/O 173 6 VCC 7 I/O 174 8 I/O 175 9 I/O 176 10 I/O 177 11 I/O 178 12 I/O ...

Page 14

Signal Configuration ispLSI 3192 272-Ball BGA I/O I/O I/O I/O I/O I/O A 116 117 121 122 125 128 I/O I/O I/O I/O I 115 118 ...

Page 15

Part Number Description ispLSI 3192 Device Family Device Number Speed f 100 = 100 MHz max MHz max Ordering Information ...

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