F25L008A-100DG ESMT [Elite Semiconductor Memory Technology Inc.], F25L008A-100DG Datasheet - Page 5
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F25L008A-100DG
Manufacturer Part Number
F25L008A-100DG
Description
8Mbit (1Mx8) 3V Only Serial Flash Memory
Manufacturer
ESMT [Elite Semiconductor Memory Technology Inc.]
Datasheet
1.F25L008A-100DG.pdf
(31 pages)
ESMT
TOP
BOTTOM
Block Protection (BP2, BP1, BP0)
The Block-Protection (BP2, BP1, BP0) bits define the size of the
memory area, as defined in Table2 to be software protected
against any memory Write (Program or Erase) operations. The
Write-Status-Register (WRSR) instruction is used to program the
BP2, P1, BP0 bits as long as
Block-Protection-Look (BPL) bit is 0. Chip-Erase can only be
executed if Block-Protection bits are all 0. After power-up, BP2,
BP1 and BP0 are set to1.
Elite Semiconductor Memory Technology Inc.
2
1
0
Protection Level
Protection Level
Bottom 1/16
Bottom 1/8
Bottom 1/4
Bottom 1/2
Upper 1/16
All Blocks
All Blocks
All Blocks
All Blocks
All Blocks
All Blocks
Upper 1/8
Upper 1/4
Upper 1/2
0
0
47
32
31
16
15
0
:
:
:
Table2 : F25L008A Block Protection Table
4KB
4KB
4KB
4KB
4KB
4KB
:
:
:
BP2
BP2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Status Register Bit
Status Register Bit
WP
BP1
BP1
is high or the
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
01F000H – 01FFFFH
00F000H – 00FFFFH
020000H – 020FFFH
010000H – 010FFFH
000000H – 000FFFH
02F000H – 02FFFFH
BP0
BP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
:
:
:
Block Protection Lock-Down (BPL)
-Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP2, BP1, and BP0 bits. When the
value is “Don’t Care”. After power-up, the BPL bit is reset to 0.
Block Range
Block Range
WP
WP pin is driven high (V
Block 12~15
Block 14~15
Block 0~15
Block 0~15
Block 8~15
Block 0~15
Block 0~15
Block 0~15
Block 0~15
Block 0~3
Block 0~1
Block 0~7
Block 15
Block 0
None
None
pin driven low (V
Protected Memory Area
Protected Memory Area
0
0
0
0
0
0
1
0
0
C0000H – FFFFFH
E0000H – FFFFFH
00000H – FFFFFH
00000H – 3FFFFH
00000H – FFFFFH
F0000H – FFFFFH
80000H – FFFFFH
00000H – FFFFFH
00000H – FFFFFH
00000H – FFFFFH
00000H – FFFFFH
00000H – 0FFFFH
00000H – 1FFFFH
00000H – 7FFFFH
Publication Date: May. 2007
Address Range
Address Range
IH
0
1
0
IL
), the BPL bit has no effect and its
), enables the Block-Protection
Revision:
None
None
F25L008A
1.4
5/31