HN58X2402SFPIAG RENESAS [Renesas Technology Corp], HN58X2402SFPIAG Datasheet - Page 7

• Manufacturer Part Number: HN58X2402SFPIAG
• Manufacturer: RENESAS [Renesas Technology Corp]

HN58X2402SFPIAG/HN58X2404SFPIAG
Device Address (A0, A1, A2)
UP to eight devices for 2k, four devices for 4k, can be addressed on the same bus by setting the levels on these pins to
different combinations. The levels on these pins are compared with the device address code which are input through
the SDA pin. The device is selected if the compare is successfully done. These pins are internally pulled-down to V
The device read these pins as Low if unconnected. As for 4k, it is unnecessary for the A0 pin to be connected because
the corresponding device address code is used as memory address a8.
Pin Connections for A0 to A2
Notes: 1. “V
Write Protect (WP)
When the Write Protect pin (WP) is high, the write protections feature is enabled and operates as shown in the
following table. When the WP is low, write operations for all memory array are allowed. The read operation is always
activated irrespective of the WP pin status. The WP pin is internally pull-down to V
memory array are allowed if unconnected.
Write Protect Area
Rev.4.00, Jul.13.2005, page 7 of 16
Memory size
2k bit
4k bit
2. × = Don’t care (Open is also approval.)
unconnected.
WP pin status
CC
/V
Max connect
SS
V
V
” means that the device address pins are connected to V
IH
number
IL
8
4
V
V
CC
CC
A2
/V
/V
SS
SS
Pin connection
*
1
V
V
CC
CC
A1
/V
/V
SS
SS
Entire (2k bit)
V
2k bit
CC
×*
A0
/V
2
SS
Use A0 for memory address a8
Normal read/write operation
Write protect area
CC
or V
SS
SS
. These pins are V
. Write operations for all
Notes
Entire (4k bit)
4k bit
SS
if
SS
.