A29L008ATV-70 AMICC [AMIC Technology], A29L008ATV-70 Datasheet - Page 16

• Manufacturer Part Number: A29L008ATV-70
• Description: 1M X 8 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
• Manufacturer: AMICC [AMIC Technology]

I/O
(October, 2006, Version 1.0)
RY/
The RY/
indicates whether an Embedded algorithm is in progress or
complete. The RY/
the final
RY/
tied together in parallel with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device is
ready to read array data (including during the Erase
Suspend mode), or is in the standby mode.
Table 6 shows the outputs for RY/
Timings”, “Timing Waveforms for Program Operation” and
“Timing Waveforms for Chip/Sector Erase Operation” for
more information.
I/O
Toggle Bit I on I/O
or Erase algorithm is in progress or complete, or whether the
device has entered the Erase Suspend mode. Toggle Bit I
may be read at any address, and is valid after the rising edge
of the final
program or erase operation), and during the sector erase
time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause I/O
(The system may use either
cycles.) When the operation is complete, I/O
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O
approximately 100µs, then returns to reading array data. If
not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use I/O
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O
device enters the Erase Suspend mode, I/O
However, the system must also use I/O
sectors are erasing or erase-suspended. Alternatively, the
system can use I/O
Polling").
If a program address falls within a protected sector, I/O
toggles for approximately 2µs after the program command
sequence is written, then returns to reading array data.
I/O
and stops toggling once the Embedded Program algorithm is
complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on I/O
algorithm, and to the Toggle Bit Timings figure in the "AC
Characteristics" section for the timing diagram. The I/O
I/O
graphical form. See also the subsection on " I/O
II".
The "Toggle Bit II" on I/O
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
6
6
2
6
BY : Read/ Busy
BY
: Toggle Bit II
: Toggle Bit I
also toggles during the erase-suspend-program mode,
figure shows the differences between I/O
is an open-drain output, several RY/
BY
WE
WE
is a dedicated, open-drain output pin that
pulse in the command sequence. Since
pulse in the command sequence (prior to the
6
BY
indicates whether an Embedded Program
7
6
. Refer to Figure 6 for the toggle bit
(see the subsection on " I/O
status is valid after the rising edge of
6
2
, when used with I/O
and I/O
OE
or
BY
2
CE
together to determine
6
. Refer to “
2
toggles. When the
to control the read
to determine which
6
6
BY
stops toggling.
6
stops toggling.
2
2
toggles for
pins can be
: Toggle Bit
and I/O
6
6
, indicates
to toggle.
RESET
7
:
Data
2
6
vs.
in
6
15
I/O
I/O
exceeded a specified internal pulse count limit. Under these
conditions I/O
indicates the program or erase cycle was not successfully
completed.
The I/O
program a "1 "to a location that is previously programmed to
"0." Only an erase operation can change a "0" back to a "1."
Under this condition, the device halts the operation, and
when the operation has exceeded the timing limits, I/O
produces a "1."
Under both these conditions, the system must issue the
reset command to return the device to reading array data.
sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the final
I/O
those sectors that have been selected for erasure. (The
system may use either
cycles.) But I/O
actively erasing or is erase-suspended. I/O
indicates whether the device is actively erasing, or is in Erase
Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and
mode information. Refer to Table 6 to compare outputs for
I/O
Figure 6 shows the toggle bit algorithm in flowchart form, and
the section " I/O
also the " I/O
Bit Timings figure for the toggle bit timing diagram. The I/O
vs. I/O
graphical form.
Reading Toggle Bits I/O
Refer to Figure 6 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
I/O
toggle bit is toggling. Typically, a system would note and
store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of the
toggle bit with the first. If the toggle bit is not toggling, the
device has completed the program or erase operation. The
system can read array data on I/O
read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O
on I/O
whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as I/O
is no longer toggling, the device has successfully completed
the program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and the
system must write the reset command to return to reading
array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and I/O
system may continue to monitor the toggle bit and I/O
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Figure
6).
5
2
2
7
5
: Exceeded Timing Limits
and I/O
- I/O
toggles when the system reads at addresses within
indicates whether the program or erase time has
6
5
). If it is, the system should then determine again
5
figure shows the differences between I/O
failure condition may appear if the system tries to
0
6
at least twice in a row to determine whether a
.
6
5
: Toggle Bit I" subsection. Refer to the Toggle
produces a "1." This is a failure condition that
2
2
: Toggle Bit II" explains the algorithm. See
cannot distinguish whether the sector is
WE
AMIC Technology, Corp.
OE
pulse in the command sequence.
6
, I/O
A29L008A Series
or
5
2
went high. If the toggle bit
CE
7
5
5
is high (see the section
has not gone high. The
- I/O
to control the read
0
6
, by comparison,
on the following
2
and I/O
6
in
5
2
5