A29L008ATV-70 AMICC [AMIC Technology], A29L008ATV-70 Datasheet - Page 6

• Manufacturer Part Number: A29L008ATV-70
• Description: 1M X 8 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
• Manufacturer: AMICC [AMIC Technology]

Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the
selects the device.
data to the output pins.
during read operation. The internal state machine is set for
reading array data upon device power-up, or after a
hardware reset. This ensures that no spurious alteration of
the memory content occurs during the power transition. No
command is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data
on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to the
Read Operations Timings diagram for the timing waveforms,
l
current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive
facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to
program a word or byte, instead of four. The “
Program Command Sequence” section has details on
programming data to the device using both standard and
Unlock Bypass command sequence. An erase operation can
erase one sector, multiple sectors, or the entire device. The
Sector Address Tables indicate the address range that each
sector occupies. A "sector address" consists of the address
inputs required to uniquely select a sector. See the
"Command Definitions" section for details on erasing a sector
or the entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on I/O
read cycle timings apply in this mode. Refer to the
"Autoselect Mode" and "Autoselect Command Sequence"
sections for more information.
I
current
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O
specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section for
timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it can
place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in
the high impedance state, independent of the
(October, 2006, Version 1.0)
OE
CC1
CC2
CE
in the DC Characteristics table represents the active
to V
in the DC Characteristics table represents the active
7
and
- I/O
IH
specification
. The device features an Unlock Bypass mode to
OE
0
. Standard read cycle timings and I
pins to V
OE
WE
for
is the output control and gates array
IL
.
should remain at V
the
CE
write
is the power control and
WE
and
mode.
7
- I/O
OE
CE
IH
0
input.
to V
all the time
. Standard
The
CC
IL
, and
read
"AC
5
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for t
sleep mode is independent of the
signals. Standard address access timings provide new data
when addresses are changed. While in sleep mode, output
data is latched and always available to the system. I
DC Characteristics table represents the automatic sleep
mode current specification.
The device enters the CMOS standby mode when the
more restricted voltage range than V
are held at V
in the standby mode, but the standby current will be greater.
The device requires the standard access time (t
is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
I
standby current specification.
Automatic Sleep Mode
Output Disable Mode
When the
disabled. The output pins are placed in the high impedance
state.
The RESET pin provides a hardware method of resetting
the device to reading array data. When the system drives the
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the RESET pulse. The device also resets the
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET pulse.
When RESET is held at VSS ± 0.3V, the device draws
CMOS standby current (I
within VSS ± 0.3V, the standby current will be greater.
The RESET pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
If RESET is asserted during a program or erase operation,
the RY/
operation is complete, which requires a time t
Embedded Algorithms). The system can thus monitor
RY/
complete. If RESET is asserted when a program or erase
operation is not executing (RY/
operation is completed within a time of t
Embedded Algorithms). The system can read data t
the RESET pin return to V
Refer to the AC Characteristics tables for RESET
parameters and diagram.
RESET pins are both held at VCC ± 0.3V. (Note that this is a
RESET
RESET pin low for at least a period of t
CC3
and I
BY
BY
CC4
: Hardware Reset Pin
to determine whether the reset operation is
OE
pin remains a “0” (busy) until the internal reset
IH
in the DC Characteristics tables represent the
, but not within VCC ± 0.3V, the device will be
input is at V
CC4
AMIC Technology, Corp.
IH
.
). If RESET is held at V
IH
, output from the device is
A29L008A Series
BY
ACC
CE
IH
pin is “1”), the reset
+30ns. The automatic
,
.) If
WE
READY
CE
and
RP
READY
, the device
and RESET
CE
OE
(not during
) before it
IL
CC4
RH
but not
(during
control
CE
in the
after
&