HN58X24128FPIAG RENESAS [Renesas Technology Corp], HN58X24128FPIAG Datasheet - Page 9
![no-image](/images/no-image-200.jpg)
HN58X24128FPIAG
Manufacturer Part Number
HN58X24128FPIAG
Description
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HN58X24128FPIAG.pdf
(22 pages)
- Current page: 9 of 22
- Download datasheet (80Kb)
Pin Function
Serial Clock (SCL)
The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge
clock data into EEPROM device and negative edge clock data out of each device. Maximum clock rate is
400 kHz.
Serial Input/Output Data (SDA)
The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that
pin is open-drain driven structure. Use proper resistor value for your system by considering V
the SDA pin capacitance. Except for a start condition and a stop condition which will be discussed later,
the SDA transition needs to be completed during SCL low period.
Data Validity (SDA data change timing waveform)
Note:
SCL
SDA
High-to-low and low-to-high change of SDA should be done during SCL low periods.
change
HN58X24128FPIAG/HN58X24256FPIAG
Data
change
Data
OL
, I
OL
and
7
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