A29L160TG-120 AMICC [AMIC Technology], A29L160TG-120 Datasheet
A29L160TG-120
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A29L160TG-120 Summary of contents
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Preliminary Document Title Bit / Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory Revision History Rev. No. History 0.0 Initial issue PRELIMINARY (July, 2002, Version 0. Bit / ...
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Preliminary Features n Single power supply operation - Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications - Regulated voltage range: 3.0 to 3.6 volt read and write operations for compatibility with high performance 3.3 ...
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General Description The A29L160 is a 16Mbit, 3.0 volt-only Flash memory organized as 2,097,152 bytes of 8 bits or 1,048,576 words of 16 bits each. The 8 bits of data appear on I/O bits of data appear on I/O ~I/O ...
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Pin Configurations n SOP RESET A18 43 A19 2 A17 A10 A11 A12 A3 8 A13 37 A2 A14 9 36 ...
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Block Diagram RY/BY VCC VSS RESET State WE Control BYTE Command Register CE OE VCC Detector A0-A19 Pin Descriptions A0 - A19 I/O I/O (A-1) 15 RESET PRELIMINARY (July, 2002, Version 0.0) Sector Switches Erase Voltage Generator PGM Voltage Generator ...
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Absolute Maximum Ratings* Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . Ambient Temperature with Power Applied . . ...
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Word/Byte Configuration The BYTE pin determines whether the I/O pins I/O operate in the byte or word configuration. If the is set at logic ”1”, the device is in word configuration, I/O I/O are active and controlled ...
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Output Disable Mode When the OE input output from the device is IH disabled. The output pins are placed in the high impedance state. RESET : Hardware Reset Pin The RESET pin provides a hardware method ...
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Table 2. A29L160 Top Boot Block Sector Address Table Sector A19 A18 A17 A16 SA0 SA1 SA2 SA3 SA4 SA5 ...
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Table 3. A29L160 Bottom Boot Block Sector Address Table Sector A19 A18 A17 A16 SA0 SA1 SA2 SA3 SA4 SA5 ...
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Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on I/O - I/O . This mode is primarily 7 0 intended for programming equipment to automatically match a device to be ...
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Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors possible to determine whether a sector is ...
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START PLSCNT=1 RESET=V ID Wait Temporary Sector First Write Unprotect Mode Cycle=60h? Yes Set up sector address Sector Protec: Write 60h to sector address with A6=0, A1=1, A0=0 Wait 150 us Verify Sector Protect: Write 40h to ...
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Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ...
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Addresses Addresses (Word Mode) (Byte Mode) 1Bh 36h 1Ch 38h 1Dh 3Ah 1Eh 3Ch 1Fh 3Eh 20h 40h 21h 42h 22h 44h 23h 46h 24h 48h 25h 4Ah 26h 4Ch Addresses Addresses (Word Mode) (Byte Mode) 27h 4Eh 28h 50h ...
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Table 8 Primary Vendor-Specific Extended Query Addresses Addresses (Word Mode) (Byte Mode) 40h 80h 41h 82h 42h 84h 43h 86h 44h 88h 45h 8Ah 46h 8Ch 47h 8Eh 48h 90h 49h 92h 4Ah 94h 48h 96h 4Ch 98h PRELIMINARY (July, ...
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Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence ...
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START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data ? No Increment Address Last Address ? Programming Completed Note : See the appropriate Command Definitions table for program command sequence. Figure 3. Program ...
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Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor I/O . Any command other than Sector ...
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Command Sequence (Note 1) Read (Note 6) 1 Reset (Note 7) 1 Word Manufacturer ID 4 Byte Word Device ID, 4 Byte Top Boot Block Word Device ID, 4 Bottom Boot Block Byte Word Continuation ID 4 Byte Word Sector ...
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Note: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all bus cycles are write operation. 4. Address bits A19 - A11 are don't cares for ...
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Write Operation Status Several bits, I/O , I/O , I/O , I the A29L160 to determine the status of a write operation. Table 10 and the following subsections describe the functions of these ...
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BY : Read/ Busy RY/ The RY dedicated, open-drain output pin that indicates whether an Embedded algorithm is in progress or complete. The RY/ BY status is valid after the rising edge of the final WE pulse ...
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I/O : Exceeded Timing Limits 5 I/O indicates whether the program or erase time has 5 exceeded a specified internal pulse count limit. Under these conditions I/O produces a "1." This is a failure condition 5 that indicates the program ...
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Operation Standard Embedded Program Algorithm Mode Embedded Erase Algorithm Erase Reading within Erase Suspend Suspended Sector Mode Reading within Non-Erase Suspend Sector Erase-Suspend-Program Notes: 1. I/O and I/O require a valid address when reading status information. Refer to the appropriate ...
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DC Characteristics CMOS Compatible Parameter Parameter Description Symbol I Input Load Current Input Load Current LIT I Output Leakage Current LO VCC Active Read Current I CC1 (Notes 1, 2) VCC Active Write (Program/Erase) I CC2 Current ...
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DC Characteristics (continued) Zero Power Flash 500 1000 Note: Addresses are switching at 1MHz I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 Note ...
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AC Characteristics Read Only Operations Parameter Symbols JEDEC Std t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV CE Output Enable to Output Delay ...
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AC Characteristics Hardware Reset ( RESET ) Parameter JEDEC Std RESET Pin Low (During Embedded t READY Algorithms) to Read or Write (See Note) RESET Pin Low (Not During Embedded t READY Algorithms) to Read or Write (See Note) t ...
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Temporary Sector Unprotect Parameter JEDEC Std t V Rise and Fall Time (See Note) VIDR ID RESET Setup Time for Temporary Sector t RSP Unprotect Note: Not 100% tested. Temporary Sector Unprotect Timing Diagram 12V RESET t ...
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AC Characteristics Word/Byte Configuration ( BYTE ) Parameter JEDEC Std t t ELFL/ ELFH CE BYTE to BYTE Switching Low to Output High-Z t FLQZ BYTE Switching High to Output Active t HQV BYTE Timings for Read Operations CE OE ...
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AC Characteristics Erase and Program Operations Parameter JEDEC Std t Write Cycle Time (Note 1) t AVAV WC Address Setup Time t t AVWL AS Address Hold Time t t WLAX Data Setup Time DVWH DS t ...
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Timing Waveforms for Program Operation Program Command Sequence (last two cycles Addresses 555h Data RY/BY t VCS VCC Note : program addrss program data, Dout is the true ...
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Timing Waveforms for Chip/Sector Erase Operation Erase Command Sequence (last two cycles Addresses 2AAh Data RY/BY t VCS VCC Note : Sector Address (for Sector Erase Valid Address ...
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Timing Waveforms for Data Polling (During Embedded Algorithms Addresses VA t ACC OEH WE I/O 7 I/O - I/O High BUSY RY/BY Note : VA = Valid Address. ...
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Timing Waveforms for Toggle Bit (During Embedded Algorithms Addresses VA t ACC OEH WE I/O , I/O High BUSY RY/BY Note Valid Address; not required for ...
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Timing Waveforms for Sector Protect/Unprotect RESET SA, A6, A1, A0 Sector Protect/Unprotect 60h Data 1us Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0 PRELIMINARY (July, 2002, Version ...
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Timing Waveforms for I/O vs. I/O 2 Enter Erase Embedded Suspend Erasing WE Erase Erase Suspend I/O 6 I/O 2 I/O and I/O toggle with OE and Note : Both I/O and I/O toggle with OE or ...
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Timing Waveforms for Alternate CE Controlled Write Operation 555 for program 2AA for erase Addresses Data for program 55 for erase RESET RY/BY Note : 1. ...
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Latch-up Characteristics Input Voltage with respect to VSS on all I/O pins VCC Current Input voltage with respect to VSS on all pins except I/O pins (including A9, OE and RESET ) Includes all pins except VCC. Test conditions: VCC ...
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Test Conditions Test Specifications Test Condition Output Load Output Load Capacitance, C (including jig capacitance) L Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels Test Setup Device Under Test PRELIMINARY ...
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... A29L160TM-120 A29L160TV-120 120 A29L160TG-120 Bottom Boot Sector Flash Access Time Part No. (ns) A29L160UM-70 A29L160UV-70 70 A29L160TG-70 A29L160UM-90 A29L160UV-90 90 A29L160TG-90 A29L160UM-120 A29L160UV-120 120 A29L160TG-120 PRELIMINARY (July, 2002, Version 0.0) Active Read Program/Erase Current Current Typ. (mA) Typ. (mA Active Read Program/Erase Current Current Typ ...
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Package Information SOP 44L Outline Dimensions Seating Plane Symbol Notes: 1. The maximum value of dimension D includes ...
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Package Information TSOP 48L (Type I) Outline Dimensions 1 24 Detail "A" Symbol Notes: 1. The maximum value of dimension D includes end flash. 2. ...
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Package Information 48 Balls CSP ( mm) Outline Dimensions (48TFBGA Ball*A1 CORNER C 0.10 C PRELIMINARY (July, 2002, Version 0.0) TOP VIEW BOTTOM VIEW ...