A29L160TG-120 AMICC [AMIC Technology], A29L160TG-120 Datasheet - Page 22

• Manufacturer Part Number: A29L160TG-120
• Description: 2M X 8 Bit / 1M X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
• Manufacturer: AMICC [AMIC Technology]

Write Operation Status
Several bits, I/O
in the A29L160 to determine the status of a write operation.
Table 10 and the following subsections describe the
functions of these status bits. I/O
offer a method for determining whether a program or erase
operation is complete or in progress. These three bits are
discussed first.
I/O
The
whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend.
pulse in the program or erase command sequence.
During the Embedded Program algorithm, the device
outputs on I/O
to I/O
Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to
I/O
valid status information on I/O
within a protected sector,
approximately 2 s, then the device returns to reading array
data.
During the Embedded Erase algorithm,
produces a "0" on I/O
algorithm is complete, or if the device enters the Erase
Suspend mode,
analogous to the complement/true datum output described
for the Embedded Program algorithm: the erase function
changes all the bits in a sector to "1"; prior to this, the
device outputs the "complement," or "0." The system must
provide an address within any of the sectors selected for
erasure to read valid status information on I/O
After an erase command sequence is written, if all sectors
selected for erasing are protected,
active for approximately 100 s, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
When the system detects I/O
complement to true data, it can read valid data at I/O
on the following read cycles. This is because I/O
change asynchronously with I/O
(
Embedded Algorithms) figure in the "AC Characteristics"
section illustrates this. Table 10 shows the outputs for
algorithm.
PRELIMINARY
Data
Data
OE
7
7
. The system must provide the program address to read
: Data Polling
Data
) is asserted low. The
7
Polling is valid after the rising edge of the final
. This I/O
Polling on I/O
Polling bit, I/O
7
7
the complement of the datum programmed
2
Data
, I/O
status also applies to programming during
(July, 2002, Version 0.0)
3
7
, I/O
. Figure 5 shows the
Polling produces a "1" on I/O
7
Data
. When the Embedded Erase
7
5
, indicates to the host system
, I/O
Data
7
. If a program address falls
6
0
Polling on I/O
7
, I/O
- I/O
7
has changed from the
, I/O
Polling Timings (During
Data
7,
6
RY/
while Output Enable
6
and RY/
Polling on I/O
BY
Data
7
7
Data
.
are provided
is active for
BY
7
.This is
Polling
Polling
7
7
- I/O
each
WE
may
7
is
0
21
Note :
1. VA = Valid address for programming. During a sector
2. I/O
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
I/O
No
7
7
should be rechecked even if I/O
may change simultaneously with I/O
Figure 5. Data Polling Algorithm
Read I/O
Read I/O
Address = VA
Address = VA
I/O
I/O
I/O
START
7
7
FAIL
= Data ?
= Data ?
5
= 1?
7
7
AMIC Technology, Inc.
-I/O
Yes
- I/O
No
No
0
0
A29L160 Series
5
Yes
= "1" because
Yes
5
.
PASS