M66256 Mitsubishi, M66256 Datasheet - Page 2

• Manufacturer Part Number: M66256
• Description: 5120 x 8-BIT LINE MEMORY (FIFO)
• Manufacturer: Mitsubishi

FUNCTION
When write enable input WE is “L”, the contents of data inputs
D
edge of write clock input WCK. At this time, the write address
counter is also incremented simultaneously.
The write function given below are also performed in synchro-
nization with rise edge of WCK.
When WE is “H”, a write operation to memory is inhibited and
the write address counter is stopped.
When write reset input WRES is “L”, the write address counter
is initialized.
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
2
V
V
V
P
T
V
GND
T
V
V
V
V
I
I
I
I
I
C
C
0
IH
IL
OZH
OZL
CC
stg
opr
CC
I
O
d
CC
IH
IL
OH
OL
I
O
to D
Symbol
Symbol
Symbol
7
are written into memory in synchronization with rise
Supply voltage
Input voltage
Output voltage
Maximum power dissipation
Storage temperature
Supply voltage
Supply voltage
Operating ambient temperature
“H” input voltage
“L” input voltage
“H” output voltage
“L” output voltage
“H” input current
“L” input current
Off state “H” output current
Off state “L” output current
Operating mean current dissipa-
tion
Input capacitance
Off state output capacitance
Parameter
Parameter
Parameter
(T
a
(T
= 0 ~ 70 C, unless otherwise noted)
a
= 0 ~ 70 C, V
I
I
V
V
V
V
V
t
f = 1MHz
f = 1MHz
OH
OL
WCK
I
I
O
O
I
= V
= GND
= V
CC
= V
= GND
= 4mA
= –4mA
, t
= 5V
CC
CC
RCK
CC
, GND, Output open
= 25ns
10%, GND = 0V)
Test conditions
A value based on GND pin
T
a
Min.
= 25 C
4.5
WE, WRES, WCK, RE,
RRES, RCK,
D
WE, WRES, WCK, RE,
RRES, RCK,
D
When read enable input RE is “L”, the contents of memory are
output to data outputs Q
edge of read clock input RCK. At this time, the read address
counter is also incremented simultaneously.
The read functions given below are also performed in syn-
chronization with rise edge of RCK.
When RE is “H”, a read operation from memory is inhibited
and the read address counter is stopped. The outputs are in
the high impedance state.
When read reset input RRES is “L”, the read address counter
is initialized.
0
0
0
~ D
~ D
Conditions
7
7
Limits
Typ.
5
0
Max.
5.5
70
V
5120
CC
Min.
0
2.0
–0.8
MITSUBISHI DIGITAL ASSP
to Q
Unit
–0.5 ~ V
–0.5 ~ V
V
V
C
8-BIT LINE MEMORY (FIFO)
7
–0.5 ~ +7.0
–65 ~ 150
in synchronization with rise
Ratings
Limits
Typ.
440
CC
CC
+ 0.5
+ 0.5
M66256FP
Max.
0.55
–1.0
–5.0
0.8
1.0
5.0
80
10
15
Unit
mW
Unit
mA
mA
mA
mA
mA
pF
pF
V
V
V
V
V
V
V
C