ISL6527 Intersil Corporation, ISL6527 Datasheet - Page 8

• Manufacturer Part Number: ISL6527
• Description: Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
• Manufacturer: Intersil Corporation

Application Guidelines
Layout Considerations
Layout is very important in high frequency switching
converter design. With power devices switching efficiently at
300kHz or 600kHz, the resulting current transitions from one
device to another cause voltage spikes across the
interconnecting impedances and parasitic circuit elements.
These voltage spikes can degrade efficiency, radiate noise
into the circuit, and lead to device over-voltage stress.
Careful component layout and printed circuit board design
minimizes the voltage spikes in the converters.
As an example, consider the turn-off transition of the PWM
MOSFET. Prior to turn-off, the MOSFET is carrying the full
load current. During turn-off, current stops flowing in the
MOSFET and is picked up by the lower MOSFET. Any
parasitic inductance in the switched current path generates
a large voltage spike during the switching interval. Careful
component selection, tight layout of the critical
components, and short, wide traces minimizes the
magnitude of voltage spikes.
There are two sets of critical components in a DC-DC
converter using the ISL6527. The switching components are
the most critical because they switch large amounts of
energy, and therefore tend to generate large amounts of
noise. Next are the small signal components which connect
to sensitive nodes or supply critical bypass current and
signal coupling.
A multi-layer printed circuit board is recommended. Figure 4
shows the connections of the critical components in the
converter. Note that capacitors C
represent numerous physical capacitors. Dedicate one solid
layer, usually a middle layer of the PC board, for a ground
plane and make all critical component ground connections
with vias to this layer. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Keep the metal runs from the
PHASE terminals to the output inductor short. The power
plane should support the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes. Use the remaining printed
circuit layers for small signal wiring. The wiring traces from
the GATE pins to the MOSFET gates should be kept short
and wide enough to easily handle the 1A of drive current.
The switching components should be placed close to the
ISL6527 first. Minimize the length of the connections between
the input capacitors, C
them nearby. Position both the ceramic and bulk input
capacitors as close to the upper MOSFET drain as possible.
Position the output inductor and output capacitors between
the upper MOSFET and lower MOSFET and the load.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
IN
, and the power switches by placing
8
IN
and C
OUT
could each
ISL6527
components. Position the bypass capacitor, C
the VCC pin with a via directly to the ground plane. Place the
PWM converter compensation components close to the FB
and COMP pins. The feedback resistors for both regulators
should also be located as close as possible to the relevant
FB pin with vias tied straight to the ground plane as required.
Feedback Compensation
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
error amplifier (Error Amp) output (V
the oscillator (OSC) triangular wave to provide a pulse-
width modulated (PWM) wave with an amplitude of V
the PHASE node. The PWM wave is smoothed by the output
filter (L
The modulator transfer function is the small-signal transfer
function of V
Gain and the output filter (L
break frequency at F
the modulator is simply the input voltage (V
peak-to-peak oscillator voltage ∆V
OUT
FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES
) is regulated to the Reference voltage level. The
O
ISL6527
and C
CPVOUT
OUT
KEY
UGATE
PHASE
AND ISLANDS
LGATE
COMP
BOOT
O
GND
VCC
).
/V
VIA CONNECTION TO GROUND PLANE
FB
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
E/A
LC
CVCC
CBP
. This function is dominated by a DC
and a zero at F
R2
C2
CBOOT
PHASE
R4
+3.3V VIN
O
and C
D1
C1
C3
OSC
Q1
Q2
R1
O
R3
E/A
), with a double pole
ESR
.
CIN
LOUT
) is compared with
COUT
IN
. The DC Gain of
) divided by the
BP
, close to
VOUT
IN
at