HMP8117CN Intersil Corporation, HMP8117CN Datasheet
HMP8117CN
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HMP8117CN Summary of contents
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... Macrovision copy-protection bypass and detection. Ordering Information TEMP RANGE o PART NUMBER ( C) PACKAGE HMP8117CN PQFP Q80.14x20 HMPVIDEVAL/ISA Evaluation Board: ISA Frame Grabber NOTES: 1. PQFP is also known as QFP and MQFP. 2. Evaluation Board descriptions are in the Applications section. 1 January 1999 Features • ...
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HMP8117 COMPOSITE/LUMA 2 CHROMA ...
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Analog Front End Block Diagram (EXTERNAL) (INTERNAL CLAMP) VAA 1.75V INPUT TO + nmos 1 VIDEO MUX # 75 PIN 50 A 1.0 F VID1 CVBS1 7 CLAMP 1.0 F VID2 CVBS2 6 CLAMP 1.0 F Y_IN CVBS3(Y) ...
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HMP8117 4 ...
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Introduction The HMP8117 is designed to decode baseband composite or S-video NTSC and PAL signals, and convert them to either digital YCbCr or RGB data. In addition to performing the basic decoding operations, these devices include hardware to decode different ...
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Input Signal Detection If no input video signal is detected for 16 consecutive line periods, nominal video timing is generated for the previously detected or programmed video standard. A maskable interrupt is provided for the condition of “Input Signal Loss” ...
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Use of a PLL to generate a “Line Locked” CLK2 input based on the input video is not recommend. (See next section below.) Cycle Slipping and Real-Time Pixel Jitter The decoder’s digital PLL allows it to maintain lock and ...
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Y data. This may make a noisy image more pleasing to the user, although softer. Coring of the high-frequency Y data may be done to reduce low-level high frequency noise. Coring of the Y data may also be ...
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R B < 0.0812*31, G < 0.0812* (31)((R /31)/4. (63)((G /63)/4. (31)((B /31)/4.5) for R B >= 0.0812*31, G >= 0.0812* (31)(((R /31) + 0.099)/1.099 ...
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NTSC(M) LINE# 262 263 PAL(M) LINE# 259 260 VIDEO INPUT HSYNC VSYNC FIELD LINE # 621 622 623 VIDEO INPUT HSYNC VSYNC FIELD ‘EVEN’ FIELD LINE # 309 310 311 VIDEO INPUT HSYNC VSYNC FIELD ‘ODD’ FIELD BLANK and DVALID ...
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NTSC M LINES NOT ACTIVE 240 ACTIVE LINES PER FIELD (LINES 23-262) 480 ACTIVE LINES/FRAME (NTSC, PAL M) LINES 263 - 284 NOT ACTIVE 240 ACTIVE LINES PER FIELD (LINES 285 - 524) NOT ACTIVE TOTAL PIXELS ...
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Pixel Output Port Pixel data is output via the P0-P15 pins. Refer to Table 4 for the output pin definition as a function of the output mode. Refer to the section “CYCLE SLIPPING AND REAL-TIME PIXEL JITTER” for PLL and ...
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CLK DVALID BLANK P15- P7-P0 Cb0 t DVLD NOTES the first active luminance pixel data of a line cycle due to the 4:2:2 subsampling. 9. BLANK is asserted per Figure 7. FIGURE 10. ...
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CLK DVALID P15-P8 P7-P0 NOTES: 11 the first active luminance pixel of a line the 4:2:2 subsampling. 12. BLANK is asserted per Figure 7. 13. DVALID is asserted for every valid pixel during both active ...
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CLK DVALID BLANK P[15- DVLD NOTES: 16 the first active luminance pixel data of a line every cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period. 17. ...
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READING THE CAPTION DATA The caption data registers may be accessed in two ways: via 2 the I C interface or as BT.656 ancillary data. CAPTIONING DISABLED ON BOTH LINES In this case, any caption data present is ignored. The ...
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The WSS odd field Read status bit is always a “0”. The WSS even field Read status bit is set to “1” after data has been transferred from the shift register to the WSS_EVEN_A and WSS_EVEN_B registers set ...
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TABLE 6. READING THE CLOSED CAPTION DATA AS BT.656 ANCILLARY DATA PIXEL OUTPUT P15 Preamble Data ID P14 Data Block Number P14 Data Word Count P14 Caption Data P14 P14 P14 P14 CRC P14 NOTES: 25. ep ...
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DETECTION OF TELETEXT The teletext decoder monitors the scan lines, looking for the 16-bit clock run-in (sometimes referred to as the clock synchronization code) used by teletext. If found, it locks to the clock run-in, the teletext data is sampled ...
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VBI DATA CAPTURE “Raw” data capture of VBI data during blanked scan lines may be optionally implemented. In this instance, the active line time of blanked scan lines are sampled at the CLK2 rate, and output onto the pixel ...
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SDA must be pulled high using external 4k pull-up resistors. The SA input pin determines the slave address for the HMP8117. If the SA pin is pulled low, the address is 1000100x . If the SA pin is pulled high ...
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DATA WRITE 1000 1000 S CHIP ADDR A SUB ADDR 0x88 DATA READ 1000 1000 (R/W) S CHIP ADDR A SUB ADDR 0x88 Control Registers SUB- ADDRESS CONTROL REGISTER 00 Product Input Format H 02 Output Format ...
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TABLE 10. CONTROL REGISTER SUMMARY (Continued) SUB- ADDRESS CONTROL REGISTER 1B Saturation H 1C Color Gain Adjust H 1D Video Gain Adjust H 1E Sharpness H 1F Host Control H 20 -23 Closed Caption Data Registers -29 ...
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BIT NUMBER FUNCTION 0 Adaptive Sync Slice This bit specifies whether to use fixed or adaptive sync slicing. Adaptive sync slicing Enable automatically determines the midpoint of the sync amplitude to determine timing Fixed sync slicing 1 = ...
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BIT NO. FUNCTION 7 Aspect Ratio 0 = Rectangular (BT.601) pixels Mode 1 = Square pixels 6 Freeze Output Setting this bit to a “1” freezes the output timing at the end of the field. Resetting this bit to a ...
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BIT NO. FUNCTION 7-6 Digital Color Gain gain control (gain = 1x) Control Select 01 = Automatic gain control 10 = Fixed gain control. (Use gain factor from Color Gain Adjust register Freeze automatic ...
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TABLE 19. SLICED VBI DATA ENABLE REGISTER BIT NO. FUNCTION 7-6 Sliced 00 = Closed caption disabled Closed Captioning 01 = Closed caption enabled for odd fields: line 21 for NTSC, line 18 for (M) PAL, or line 22 for ...
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BIT NO. FUNCTION 7 Vertical Lock This bit is read-only. Data written to this bit is ignored. Status If set to “1”, the decoder is vertically locked to the input signal. 6 Horizontal Lock This bit is read-only. Data written ...
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BIT NO. FUNCTION 7 Genlock Loss If set to “1”, this bit indicates the interrupt request was due to a loss of genlock. Interrupt Status To clear the interrupt request, a “1” must be written to this bit. 6 Input ...
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BIT NO. FUNCTION 7-0 Raw VBI Start Specifies the start of the raw VBI data sampling window in two CLK2 period steps from the Count leading edge of HSYNC. TABLE 27. RAW VBI STOP COUNT LSB REGISTER BIT NO. FUNCTION ...
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MASK MASK_18_16 (Register = Default) (Reg REGISTER BIT Mask Bit NTSC (Odd) Line NTSC (Even) Line# 290 289 288 PAL (Odd) Line PAL (Even) Line# ...
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BIT NO. FUNCTION 7-0 Video Gain Adjust This register is enabled by the selection of “fixed gain control” mode in the Analog Input Control register 05 digital gain factor which is applied to both Luma and Chroma input channels. The ...
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BIT NO. FUNCTION 7 Software Reset When this bit is set to 1, the entire device except the I like the RESET input going active. The software reset will initialize all register bits to their reset state. Once set this ...
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TABLE 46. CLOSED CAPTION_EVEN_B DATA REGISTER BIT NO. FUNCTION 15-8 Even Field If even field captioning is enabled and present, this register is loaded with the second eight bits Caption Data of caption data on line 281, 284, or 335. ...
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BIT NO. FUNCTION 7-6 Reserved 5-0 Even Field If even field WSS is enabled and present during NTSC operation, this register is loaded with the WSS CRC Data six bits of CRC information on line 283 always a ...
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BIT NO. FUNCTION 7-0 Negate BLANK This 8-bit register specifies the line number to negate BLANK each field. Output Signal For NTSC operation, it occurs on line ( odd fields and line (n + 268) on even ...
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TABLE 63. PROGRAMMABLE FRACTIONAL GAIN BIT NO. FUNCTION 7-6 Reserved Set Select PFG Enable Set to “1” to enable the recommended PFG value in bits 4-0 below. 4-0 PFG Programmable Fractional Gain (PFG). When enabled by ...
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Pinout AGND AGND CVBS3(Y) CVBS2 CVBS1 Y AGND AGND AGND AGND A/D_TEST AGND AGND AGND AGND AGND Pin Descriptions PIN PIN NAME NUMBER I/O PASSIVE CVBS1 CVBS2, 75 Term, CVBS3( AC-coupled YOUT 9 O ...
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Pin Descriptions (Continued) PIN PIN NAME NUMBER I/O PASSIVE LCAP AGND CCAP AGND P0-P15 42, 43, 45, 47-51, 54-58, O 60, 63, 64 HSYNC 71 O 10K Pullup VSYNC 70 O 10K Pullup FIELD ...
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Applications Information Direct Interface to Video Encoders Direct interface to a video encoder will induce pixel jitter in the output video and is therefore not recommended as a primary data interface. The jitter will occur with all decoder output formats, ...
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Related Application Notes Application Notes are also available on the Intersil Multimedia web site at http://www.intersil.com/mmedia. AN9644: Composite Video Separation Techniques AN9716: Wide Screen Signalling AN9717: YCbCr to RGB Considerations AN9728: BT.656 Video Interface for ICs AN9806: Advantages of the ...
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... Output Logic High Voltage Output Logic Low Voltage 42 HMP8117 Thermal Information Thermal Resistance (Typical, See Note 40) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . + 0.5V CC Maximum Power Dissipation HMP8117CN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.78W Maximum Storage Temperature Range . . . . . . . . . . -65 Maximum Junction Temperatures . . . . . . . . . . . . . . . . . . . . . .150 Maximum Lead Temperature (Soldering 10s 300 5.0V ...
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Electrical Specifications PARAMETER Input Leakage Current Input/Output Capacitance AC CHARACTERISTICS: DIGITAL I/O (EXCEPT I CLK2 Frequency CLK2 Waveform Symmetry CLK2 Pulse Width High CLK2 Pulse Width Low Data and Control Setup Time Data and Control Hold ...
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Electrical Specifications PARAMETER GENLOCK PERFORMANCE Horizontal Locking Time Long-Term horizontal Sync Lock Range Number of Missing Horizontal Syncs Before Lost Lock Declared Number of Missing Vertical Syncs Before Lost Lock Declared Long-Term Color Subcarrier Lock Range ...
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... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...