HA456 Intersil Corporation, HA456 Datasheet - Page 3

• Manufacturer Part Number: HA456
• Description: 120MHz/ Low Power/ 8 x 8 Video Crosspoint Switch
• Manufacturer: Intersil Corporation

Pin Description
44, 2, 4, 7, 9, 11,
3, 6, 17, 28, 39
22, 24, 26, 29,
31, 33, 35, 37
12, 23, 38
25, 27, 30
42, 43, 1
MQFP
13, 15
16, 32
5, 8
40
41
10
14
18
19
20
21
34
36
PIN
1, 9, 12, 23, 34
28, 30, 32, 35,
15, 17, 19, 21
37, 39, 41, 43
6, 8, 10, 13,
18, 29, 44
31, 33, 36
4, 5, 7
11, 14
22, 38
PLCC
16
20
24
25
26
27
40
42
2
3
3
D1/ SER OUT
EDGE/LEVEL
OUT7-OUT0
D0/SER IN
A2, A1, A0
SER/PAR
IN0-IN7
LATCH
NAME
DGND
AGND
WR
NC
CE
CE
V+
D3
D2
V-
No connect. Not internally connected.
Parallel Data Bit input D1 for Parallel Programming Mode. Serial Data Output (MSB of shift
register) for cascading multiple HA456s in serial programming mode. Simply connect
Serial Data Out of one HA456 to Serial Data In of another HA456 to daisy chain multiple
devices.
Parallel Data Bit Input D0 for Parallel Programming Mode. Serial Data Input (input to shift
register) for serial programming mode.
Output Channel Address Bits. These inputs select the output being programmed in parallel
programming mode.
Analog Video Input Lines.
Digital Ground. Connect both DGND pins to AGND.
A user strapped input that defines whether synchronous channel switching is edge or level
controlled. With this pin strapped high, the slave register loads from the master register
(thus changing the switch matrix state) on the rising edge of the LATCH signal. If it is
strapped low (level mode), the slave register is transparent while LATCH is low, passing
data directly from the master register to the switch state decoders. Strapping EDGE/LEVEL
and LATCH low causes the channel switch to execute on the WR rising edge (not
recommended for serial mode operation).
Positive Supply Voltage. Connect all V+ pins together and decouple each pin to AGND
(Figure 2).
A user strapped input that defines whether the serial (SER/PAR=1) or parallel
(SER/PAR=0) digital programming interface is being utilized.
Negative Supply Voltage. Connect both V- pins together and decouple each pin to AGND
(Figure 2).
WRITE Input. In serial mode, data shifts into the shift register (Master Register) LSB from
SER IN on the WR rising edge. In parallel mode, the Master Register loads with D3:0 (iff
D3:0=0000 through 1000), or the appropriate action is taken (iff D3:0=1011 through 1111),
on the WR rising edge (see Table 1).
Synchronous Channel Switch Control Input. If EDGE/LEVEL = 1, data is loaded from the
Master Register to the Slave Register on the rising edge of LATCH. If EDGE/LEVEL = 0,
data is loaded from the Master to the Slave Register while LATCH = 0. In parallel mode,
commands 1011 through 1110 execute asynchronously, on the WR rising edge, regardless
of the state of LATCH or EDGE/LEVEL. Parallel mode command 1111 executes a software
“Latch” (see Table 1).
Chip Enable. When CE = 0 and CE = 1, the WR line is enabled.
Chip Enable. When CE = 0 and CE = 1, the WR line is enabled.
Analog Video Outputs.
Analog Ground.
Parallel Data Bit Input D3 when SER/PAR = 0. D3 is unused with serial programming.
Parallel Data Bit Input D2 when SER/PAR = 0. D2 is unused with serial programming.
HA456
FUNCTION