ML6430 Micro Linear, ML6430 Datasheet - Page 16

• Manufacturer Part Number: ML6430
• Description: Genlocking Sync Generator with Digital Audio Clock for NTSC / PAL & VGA
• Manufacturer: Micro Linear

ML6430/ML6431
FUNCTIONAL DESCRIPTION
CONTROL REGISTER INFORMATION
Table 8. Default Control Register Settings for Preset Mode
REGISTER DESCRIPTION
SLEEP: Enables or disables sleep mode. When using
serial bus control, ALL registers must be programmed to
their intended state after power up to ensure correct
operation of the ML6430/ML6431.
CSR: Composite sync register bit controls whether
composite sync output is from the sync separator,
(raw C
(regenerated C
Pulse Polarity Control: The active state of output sync
pulses, blanking pulses, or clamp pulses may be
programmed to either 0 or 1 state by use of these bits.
Burst: Controls the length of Burst Gate so pulse can be
used for either burst gating in encoder applications or
back porch clamping.
16
REGISTER
PulsePol[2:0]
Clk4X
Pixel[10:0]
Burst
CSyncRaw
RawClamp
TTL Sync
WideBlank
HDelay[6:0]
Noise Gating
Test 3,1,4
External 54
Clock IN
FAud[1:0]
VCR
SLEEP
Thresh[1:0]
VGA
Div4
Fstd[2:0]
PALX
SYNC
P0: C
P1: H
P2: S
TAL
) or from the internal pulse generator
low active when 0.
active when 1, low active when 0.
active when 1, low active when 0.
CLAMP
SYNC
BLANK
SYNC
pulse output is high active when 1,
).
, and V
and B
CLAMP
BLANK
Determined by PRESET pin
Determined by PRESET pin
Determined by PRESET pin
Determined by PRESET pin
Determined by PRESET pin
pulse outputs are high
pulse outputs are high
SETTING
1000000
0, 0, 0
000
01
11
0
0
0
0
0
0
0
0
0
0
(Continued)
RawClamp: Controls the source of the S
clamp) pulse. Pulse is timed relative to incoming sync
edge, or regenerated sync edge.
PALXTAL: Controls the expected crystal frequency at the
oscillator inputs. 0 = NTSC 3.58MHz, or 1 = PAL 4.43MHz.
Thresh1,Thresh0: Selects the pixel error threshold at
which relock is initiated. Values are:
Noise Gating: Enables a 3/4 line window to lockout any
unwanted horizontal sync pulses.
VGA: Produces non-interlaced progressive scan outputs.
Div4: Controls the prescaler in the M/N loop. High means
that 4Fs external oscillator signals are expected, low
assumes a PAL or NTSC Fs crystal will be used.
VCR: Controls the gain range and locking maneuvers of
the digital loop. Provides better locking to the
unpredictability of VCR headswitches and jitter.
Blanking Width Control: The number of blanked lines in
the vertical interval is programmable to either 9 or 16.
XTAL: external Crystal Control: 0=NTSC 3.58MHz, or
1=PAL 4.43MHz, for both local crystal and external
oscillator mode.
External 54MHz Clock: This mode permits injecting a
54MHz clock (or other 4X clock) directly into the
horizontal pixel counter via the SLEEP pin. All timing
pulses are synchronous to the 54MHz clock (or other 4X
clock).
Serial Bus Control: To place the Ml6430/ML6431 in serial
mode, take P0 (Preset ) to logical '0' or ground. The serial
control system is written to by the external processor in 8-
bit bytes. Each of these bytes is partitioned into an
address (upper 4 bits of serial byte) and a data register
(lower 4 bits of serial byte). In Table 10, the Register
heading refers to the 4-bit address, and Data Bit refers to a
particular bit in the 4-bit register (Bit0 is LSB).
Pixel: Program all bits to zero to enable default values for
each standard. Otherwise use the following equation:
Test: All test bits must be programmed to zero.
0,0: 2.5 pixels
0,1: 2.5 pixels
1,0: 1.0 pixels
1,1: 4.0 pixels
P[10:0] = 2 (number of pixels per line) – 1024
CLAMP
(sync
(1)