74ABT377 Fairchild Semiconductor, 74ABT377 Datasheet

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74ABT377

Manufacturer Part Number
74ABT377
Description
Octal D-Type Flip-Flop with Clock Enable
Manufacturer
Fairchild Semiconductor
Datasheet

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© 1999 Fairchild Semiconductor Corporation
74ABT377CSC
74ABT377CSJ
74ABT377CMSA
74ABT377CMTC
74ABT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The ABT377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) input loads all flip-flops simultaneously
when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to
the LOW-to-HIGH clock transition for predictable operation.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Package Number
MSA20
MTC20
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
DS011550
Features
Pin Descriptions
Truth Table
H
X
h
I
Clock enable for address and data synchronization
applications
Eight edge-triggered D-type flip-flops
Buffered common clock
See ABT273 for master reset version
See ABT373 for transparent latch version
See ABT374 for 3-STATE version
Output sink capability of 64 mA, source capability
of 32 mA
Guaranteed latchup protection
High impedance glitch free bus loading during entire
power up and power down cycle
Non-destructive hot insertion capability
Disable time less than enable time to avoid bus
contention
LOW Voltage Level one setup time prior to the
HIGH Voltage Level one setup time prior to the
HIGH Voltage Level
Immaterial
Operating Mode
LOW-to-HIGH Clock Transition
LOW-to-HIGH Clock Transition
Package Description
Load “1”
Load “0”
Hold
(Do Nothing)
Pin Names
D
CE
CP
Q
0
0
–D
–Q
7
7

L
CP



X
Data Inputs
Clock Enable (Active LOW)
Clock Pulse Input
Data Outputs
LOW Voltage Level
LOW-to-HIGH Clock Transition
Inputs
CE
H
January 1993
Revised November 1999
h
I
I
Descriptions
D
X
X
h
I
n
www.fairchildsemi.com
No Change
No Change
Output
Q
H
L
n

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74ABT377 Summary of contents

Page 1

... MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74ABT377CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 ...

Page 3

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-OFF State in ...

Page 4

AC Electrical Characteristics (SOIC Package) Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PLH PHL n AC Operating Requirements Symbol Parameter t (H) Setup Time, HIGH S t (L) or LOW ...

Page 5

AC Loading *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load Input Pulse Requirements Amplitude 3.0V FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 5. Propagation Delay, ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body www.fairchildsemi.com Package Number M20B 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number MSA20 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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