HC4046 System Logic Semiconductor, HC4046 Datasheet - Page 10

• Manufacturer Part Number: HC4046
• Description: Phase-Locked Loop
• Manufacturer: System Logic Semiconductor

consists of four flip-flops and some gating logic, a
three state output and a phase pulse output as shown
in Figure 6. This comparator acts only on the positive
edges of the input signals and is independent of duty
cycle.
to force the PLL into lock with 0 phase difference
between the VCO output and the signal input positive
waveform edges. Figure 8 shows some typical loop
waveforms. First assume that SIG
COMP
be increased to bring its leding edge into proper phase
alignment. Thus the phase detector 2 output is set
high. This will cause the loop filter to charge up the
VCO input, increasing the VCO frequency. Once the
leading edge of the COMP
goes TRI-STATE holding the VCO input at the loop
filter voltage. If the VCO still lags the SIG
phase detector will again charge up the VCO input for
the time between the leading edges of both waveforms.
leading edge of the VCO is seen; the output of the
phase comparator goes low. This discharges the loop
filter until the leading edge of the SIG
which time the output disables itself again. This has
the effect of slowing down the VCO to again make the
rising edges of both waveforms coincidental.
running either slower or faster than the SIG
running slower the phase detector will see more SIG
rising edges and so the output of the phase
comparator will be high a majority of the time, raising
the VCO’s frequency. Conversely, if the VCO is
running faster than the SIG
detector will be low most of the time and the VCO’s
output frequency will be decreased.
output of phase comparator 2 will be disabled except
for minor corrections at the leading edge of the
waveforms. When PC
output is high. This output can be used to determine
when the PLL is in the locked condition.
characteristics. Over the entire VCO frequency range
there is no phase difference between the COMP
the SIG
capture range. Minimal power was consumed in the
loop filter since in lock the detector output is a high
impedance. When no SIG
IN
Phase Comparator 2
This detector is a digital memory network. It
Phase comparator 2 operates in such a way as
If the VCO leads the SIG
When the PLL is out of lock, the VCO will be
As one can see, when the PLL is locked, the
This
IN
. This means that the VCO’s frequency must
. The lock range of the PLL is the same as the
detector
2
IN
is TRI-STATED, the PCP
has
is present, the detector will
IN
is detected, the output
IN
, the output of the
several
IN
IN
IN
then when the
is leading the
is detected at
IN
interesting
IN
then the
. If it is
IN
and
IN
see only VCO leading edges, so the comparator output
will stay low, forcing the VCO to f
causing the PLL to unlock. If a noise pulse is seen on
the SIG
edge of the SIG
until the VCO leding edge is see, potentially for an
entire SIG
speed up during that time. When using PC
of that phase detector would be disturbed for only the
short duration of the noise spike and would cause less
upset.
phase detector using an RS flip-flop as shown in
Figure 6. When the PLL is using this comparator, the
loop is controlled by positive signal transitions and
the duty factors of SIG
important. It has some similar characteristics to the
edge sensitive comparator. To see how this detector
works, assume input pulses are applied to the SIGN
and COMP
leads the COMP
loop filter and cause the VCO to speed up, bringing the
comparator into phase with the SIG
between SIG
is 180 at f
for PC
to the VCO .When no SIG
forced to f
comparators tors should be compared to the
requirement of the system design and the appropriate
one should be used.
2
Phase comparator 2 is more susceptible to noise,
Phase Comparator 3
This is positive edge-triggered sequential
The operating characteristics of all three phase
IN
but consequently has more ripple in the signal
Figure 8. Typical Waveforms for PLL Using
Figure 9. Typical Waveforms for PLL Using
, the comparator treats it as another positive
max
IN
o
IN
. The voltage swing for PC
IN
’s as shown in Figure 9. When the SIGN
period. This would cause the VCO t o
as opposed to fmin when PC
and COMP
IN
IN
Phase Comparator 2
Phase Comparator 3
and will cause the output to go high
, the flop is set. This will charge the
TECHNICAL DATA
IN
IN
IN
is present the VCO will be
varies from 0 to 360 and
and COMP
min
IN
.
. The phase angle
3
is greater than
2
1
, the output
IN
is used.
489
are not
IN
IN