93LC66A-IP Microchip Technology, 93LC66A-IP Datasheet - Page 5

• Manufacturer Part Number: 93LC66A-IP
• Description: 4K 2.5V Microwire Serial EEPROM
• Manufacturer: Microchip Technology

3.4
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
FIGURE 3-2:
FIGURE 3-3:
 1998 Microchip Technology Inc.
CLK
DO
CLK
DO
CS
DI
CS
DI
Guaranteed at Vcc = 4.5V to +6.0V.
CSL
ERASE
). DO at logical “0” indicates that program-
HIGH-Z
HIGH-Z
ERASE TIMING
ERAL TIMING
1
1
0
1
0
1
A
1
N
A
0
N
-1
A
X
N
-2
•••
•••
3.5
The Erase All (ERAL) instruction will erase the entire
memory array to the logical “1” state. The ERAL cycle
is identical to the ERASE cycle except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS. Clocking of
the CLK pin is not necessary after the device has
entered the ERAL cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
plete.
A0
X
T
T
CSL
CSL
CSL
Erase All (ERAL)
) and before the entire ERAL cycle is com-
T
T
T
T
EC
SV
CHECK STATUS
SV
WC
CHECK STATUS
BUSY
BUSY
93LC66A/B
READY
READY
DS21209C-page 5
HIGH-Z
HIGH-Z
T
T
CZ
CZ