93AA66A Microchip Technology, 93AA66A Datasheet - Page 10
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93AA66A
Manufacturer Part Number
93AA66A
Description
(93AA66A - 93AA66C) 4K Microwire Compatible Serial EEPROM
Manufacturer
Microchip Technology
Datasheet
1.93AA66A.pdf
(24 pages)
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93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
2.9
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
For 93AA66A/B/C and 93LC66A/B/C devices, after the
last data bit is clocked into DI, the falling edge of CS
initiates the self-timed auto-erase and programming
cycle. For 93C66A/B/C devices, the self-timed auto-
erase and programming cycle is initiated by the rising
edge of CLK on the last data bit. Clocking of the CLK
pin is not necessary after the device has entered the
WRAL cycle. The WRAL command does include an
FIGURE 2-10:
FIGURE 2-11:
DS21795B-page 10
CLK
CLK
DO
V
DO
CS
CS
DI
DI
CC
must be
WRITE ALL (WRAL)
4.5V for proper operation of WRAL.
1
1
HIGH-Z
HIGH-Z
WRAL TIMING FOR 93AA AND 93LC DEVICES
WRAL TIMING FOR 93C DEVICES
0
0
0
0
0
0
1
1
X
X
•••
•••
X
X
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction
but the chip must be in the EWEN status.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
V
Dx
Dx
CC
Note:
must be
CSL
•••
•••
).
Issuing a Start bit and then taking CS low
will clear the READY/BUSY status from
DO.
D0
D0
4.5V for proper operation of WRAL.
T
T
CSL
CSL
T
WL
T
WL
BUSY
BUSY
2003 Microchip Technology Inc.
T
T
SV
SV
READY
READY
HIGH-Z
HIGH-Z
T
T
CZ
CZ