93AA66A Microchip Technology, 93AA66A Datasheet - Page 7
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93AA66A
Manufacturer Part Number
93AA66A
Description
(93AA66A - 93AA66C) 4K Microwire Compatible Serial EEPROM
Manufacturer
Microchip Technology
Datasheet
1.93AA66A.pdf
(24 pages)
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2.5
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle is
identical to the ERASE cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
‘93C’ devices where the rising edge of CLK before the
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
FIGURE 2-3:
FIGURE 2-4:
2003 Microchip Technology Inc.
CLK
CLK
DO
DO
CS
DI
CS
DI
V
CC
ERASE ALL (ERAL)
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
HIGH-Z
HIGH-Z
must be
1
4.5V for proper operation of ERAL.
1
ERAL TIMING FOR 93AA AND 93LC DEVICES
ERAL TIMING FOR 93C DEVICES
0
0
0
0
1
1
0
0
X
X
•••
•••
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
low (T
V
X
X
CC
Note:
must be
T
T
CSL
CSL
CSL
).
Issuing a Start bit and then taking CS low
will clear the READY/BUSY status from
DO.
T
EC
T
T
T
4.5V for proper operation of ERAL.
EC
SV
SV
CHECK STATUS
CHECK STATUS
BUSY
BUSY
READY
READY
DS21795B-page 7
HIGH-Z
HIGH-Z
T
T
CZ
CZ