XC1701 Xilinx, XC1701 Datasheet - Page 4

• Manufacturer Part Number: XC1701
• Description: Serial Configuration PROMs
• Manufacturer: Xilinx

XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs
Figure 2: Master Serial Mode. The one-time-programmable Serial Configuration PROM supports automatic loading of
5-4
the 3.3 k M2 Pull-Down
Resistor Overcomes the
During Configuration
but it Allows M2 to
3.3-k Resistor is
Internal Pull-Up,
* If Readback is
Series With M1
configuration programs. Multiple devices can be cascaded to support additional FPGA. An early D/P inhibits the
PROM data output one CCLK cycle before the FPGA I/Os become active.
Activated, a
be User I/O.
Required in
General-
Purpose
User I/O
RESET
Pins
(OUTPUT)
(OUTPUT)
DOUT
CCLK
DIN
•
•
•
•
•
LDC
INIT
DOUT
M2
HDC
RESET
M0 M1 PWRDWN
Other
I/O Pins
*
FPGA
Vcc
CCLK
INIT
DIN
D/P
(Low Resets the Address Pointer)
DATA
CLK
CE
OE/RESET
V CC
Vcc
OPTIONAL
Daisy-chained
FPGAs with
Different
Configurations
OPTIONAL
Slave FPGAs
with Identical
Configurations
SCP
V PP
CEO
December 10, 1997 (Version 1.1)
DATA
CLK
CE
OE/RESET
Cascaded
Memory
Serial
X8256