NCP1031 ON, NCP1031 Datasheet - Page 15

• Manufacturer Part Number: NCP1031
• Description: Low Power PWM Controller with On-Chip Power Switch and Startup Circuits for 48V Telecom Systems
• Manufacturer: ON

PWM Comparator and Latch
compares the error amplifier output (COMP) to the C
Ramp and generates a proportional duty cycle. The Power
Switch is enabled while the C
shown in Figure 35. Once the C
Power Switch is disabled. If COMP is at the bottom of the
C
While COMP increases, the duty cycle increases, until
COMP reaches the peak of the C
controller operates at maximum duty cycle.
Generator to set the PWM Latch and enable switching at the
beginning of each period. Switching is allowed while the C
Ramp is below COMP and a current limit fault is not present.
typically 150 ns. If the system is designed to operate with a
minimum ON time less than 150 ns, the converter will skip
pulses. Skipping pulses is usually not a problem, unless
operating at a frequency close to the audible range. Skipping
pulses is more likely when operating at high frequencies
during high line and minimum load condition.
EA output and the COMP pin. Under normal operation, a 220
mV offset is observed between the C
crossing points. This is not a problem as the series resistor
does not interact with the error amplifier transfer function.
Current Limit Comparator and Power Switch Circuit
Switch Circuit with control logic circuitry. The Power
Switch Circuit is designed to directly drive the converter
transformer. The characteristics of the Power Switch Circuit
are well known. Therefore, the gate drive is tailored to
control switching transitions and help limit electromagnetic
interference (EMI). The Power Switch Circuit is capable of
switching 200 V.
technology to monitor the drain current. A sense voltage is
generated by driving a sense element, R
proportional to the drain current. The sense voltage is
compared to an internal reference voltage on the
non−inverting input of the Current Limit Comparator. If the
sense voltage exceeds the reference level, the comparator
resets the PWM Latch and switching is terminated. The
NCP1030 and NCP1031 drain current limit thresholds are
0.5 A and 1.0 A, respectively.
voltage spike appears across R
Power Switch Circuit gate to source capacitance,
transformer interwinding capacitance, and output rectifier
T
The Pulse Width Modulator (PWM) Comparator
The C
The PWM Latch and Comparator propagation delay is
A series resistor is included for ESD protection between the
The NCP103x monolithically integrates a 200 V Power
The Power Switch Circuit incorporates SENSEFET
Each time the Power Switch Circuit turns ON, a narrow
Ramp, the converter operates at minimum duty cycle.
T
Charge Signal is filtered through a One Shot Pulse
SENSE
T
T
T
Ramp is below COMP as
Ramp reaches COMP, the
Ramp, at which point the
T
. The spike is due to the
Ramp and the COMP
SENSE
, with a current
NCP1030, NCP1031
http://onsemi.com
T
T
15
recovery time. This spike can cause a premature reset of the
PWM Latch. A proprietary active Leading Edge Blanking
(LEB) Circuit masks the current signal to prevent the
voltage spike from resetting the PWM Latch. The active
LEB masks the current signal until the Power Switch turn
ON transition is complete. The adaptive LEB period
provides better current limit control compared to a fixed
blanking period.
100 ns. This time is measured from when an overcurrent
fault appears at the Power Switch Circuit drain, to the start
of the turn−off transition. Propagation delay must be
factored in the transformer design to avoid transformer
saturation.
Thermal Shutdown
protect the integrated circuit in the event the maximum
junction temperature is exceeded. When activated, typically
at 150_C, the Power Switch Circuit is disabled. Once the
junction temperature falls below 105_C, the NCP103x is
allowed to resume normal operation. This feature is
provided to prevent catastrophic failures from accidental
device overheating. It is not intended to be used as a
substitute for proper heatsinking.
Application Considerations
using the NCP1030. The bias supply generates an isolated
12 V output. The circuit schematic is shown in Figure 38.
Application Note AND8119/D describes the design of the
bias supply.
35−76V
The current limit propagation delay time is typically
Internal Thermal Shutdown circuitry is provided to
A 2 W bias supply for a 48 V telecom system was designed
680p
+
−
0.022
Figure 38. 2 W Isolated Bias Supply Schematic
0.033
2.2
680p
2.2
GND
CT
VFB
COMP
10k
NCP1030
VDRAIN
VCC
0.01
UV
OV
499
1M
45k3
34k
1:2.78
MBRA160T3
0.01
MBRA160T3
2.2
22
1k30
4k99
12V
10
+
−