HIP6012 Intersil Corporation, HIP6012 Datasheet - Page 7

• Manufacturer Part Number: HIP6012
• Description: Buck and Synchronous-Rectifier Pulse-Width Modulator (PWM) Controller
• Manufacturer: Intersil Corporation

Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the HIP6012) and the impedance networks Z
and Z
a closed loop transfer function with the highest 0dB crossing
frequency (f
is the difference between the closed loop phase at f
180
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
F
F
F
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
3. Place 2
LC
Z1
Z2
FIGURE 7. VOLTAGE - MODE BUCK CONVERTER
V
o
=
(~75% F
=
=
OSC
FB
The equations below relate the compensation
-------------------------------------- -
2
----------------------------------
2
----------------------------------------------------- -
2
. The goal of the compensation network is to provide
OSC
R2 C1
ST
ND
L
0dB
R1
1
1
COMPARATOR
LC
O
COMPENSATION DESIGN
ERROR
AMP
V
HIP6012
Zero Below Filter’s Double Pole
)
Zero at Filter’s Double Pole
+
) and adequate phase margin. Phase margin
1
E/A
DETAILED COMPENSATION COMPONENTS
PWM
C
R3
O
Z
+
-
COMP
+
FB
-
C1
C3
REFERENCE
C2
2-158
+
-
R2
F
DRIVER
DRIVER
ESR
Z
REF
F
F
IN
P1
P2
=
Z
FB
=
FB
=
-------------------------------------------- -
2
----------------------------------
2
V
------------------------------------------------------ -
2
IN
PHASE
C3
ESR C
(PARASITIC)
R3 C3
R2
1
1
Z
L
IN
O
R1
R3
1
ESR
--------------------- -
C1
C1 C2
C
O
V
O
OUT
+
0dB
C2
V
OUT
and
IN
HIP6012
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high
gain peak do to the high Q factor of the output filter and is
not shown in Figure 8. Using the above guidelines should
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F
capabilities of the error amplifier. The Closed Loop Gain is
constructed on the log-log graph of Figure 8 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
the gain.
The compensation gain uses external impedance networks
Z
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
Include worst case component variations when determining
phase margin.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the
transient and slow the current load rate seen by the bulk
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
FB
100
-20
-40
-60
80
60
40
20
and Z
0
10
(R2/R1)
20LOG
IN
MODULATOR
ST
ND
to provide a stable, high bandwidth (BW) overall
100
Pole at the ESR Zero
Pole at Half the Switching Frequency
GAIN
1K
F
Z1
F
FREQUENCY (Hz)
LC
F
Z2
10K
F
P1
F
(V
ESR
100K
IN
20LOG
F
/ V
P2
OSC
P2
OPEN LOOP
ERROR AMP GAIN
1M
)
with the
COMPENSATION
GAIN
CLOSED LOOP
GAIN
10M
o
.