LM75 ON Semiconductor, LM75 Datasheet - Page 4

• Manufacturer Part Number: LM75
• Description: 2-Wire Serial Temperature Sensor and Monitor
• Manufacturer: ON Semiconductor

Serial Data (SDA)
using this pin.
Serial Clock (SCL)
INT/CMPTR
Mode, unconditionally driven active any time temperature
exceeds the value programmed into the T
INT/CMPTR will become inactive when temperature
subsequently falls below the T
and
INT/CMPTR is made active by TEMP exceeding T
unconditionally reset to its inactive state by reading any
register via the 2–wire bus. If and when temperature falls
below T
any register will clear the T
the INT/CMPTR output is unconditionally reset upon
entering Shutdown Mode. If programmed as an active–low
output, it can be wire–ORed with any number of other open
collector devices. Most systems will require a pull–up
resistor for this configuration.
power dissipation and may cause internal heating of the
LM75. To avoid affecting the accuracy of ambient
temperature readings, the pull–up resistor should be made as
large as possible. INT/CMPTR’s output polarity may be
programmed by writing to the INT/CMPTR POLARITY bit
in the CONFIG register. The default is active low.
Address (A2, A1, A0)
8–bit address. A match between the LM75’s address and the
address specified in the serial bit stream must be made to
initiate
protocol–compatible devices with other addresses may
share the same 2–wire bus.
(Set as Desired)
A typical LM75 hardware connection is shown in Figure 1.
Bidirectional. Serial data is transferred in both directions
Input. Clocks data into and out of the LM75.
Open Collector, Programmable Polarity. In Comparator
Note that current sourced from the pull–up resistor causes
Inputs. Sets the three least significant bits of the LM75
Two Wire
Interface
Address
Programmer’s
HYST
communication
, INT/CMPTR is again driven active. Reading
SDA
SCL
Figure 1. Typical Application
A 0
A 1
A 2
7
6
5
1
2
Model.)
TCN75
HYST
4
8
with
+V DD
HYST
C Bypass
interrupt. In Interrupt Mode,
setting. (See Register Set
In
3
INT/CMPTR
the
0.1
Unless Device is
Mounted Close to CPU
DETAILED OPERATING DESCRIPTION
Interrupt
m
F Recommended
LM75.
SET
register.
SET
http://onsemi.com
Mode,
Many
; it is
LM75
4
Slave Address
A5, A4, A3) are fixed to 1001[B]. The states of A2, A1 and
A0 in the serial bit stream must match the states of the A2,
A1 and A0 address inputs for the LM75 to respond with an
Acknowledge (indicating the LM75 is on the bus and ready
to accept data). The Slave Address is represented by:
LM75 Slave Address
Comparator/Interrupt Modes
the LM75 is in Comparator Mode or Interrupt Mode.
Comparator Mode is designed for simple thermostatic
operation. INT/CMPTR will go active anytime TEMP
exceeds T
will remain active until TEMP falls below T
it will reset to its inactive state. The state of INT/CMPTR is
maintained in shutdown mode when the LM75 is in
comparator mode. In Interrupt Mode, INT/CMPTR will
remain active indefinitely, even if TEMP falls below T
until any register is read via the 2–wire bus. Interrupt Mode
is better suited to interrupt driven microprocessor–based
systems. The INT/CMPTR output may be wire–OR’ed with
other interrupt sources in such systems. Note that a pull–up
resistor is necessary on this pin since it is an open–drain
output. Entering Shutdown Mode will unconditionally reset
INT/CMPTR when in Interrupt Mode.
SHUTDOWN MODE
register (CONFIG) the LM75 enters its low–power
shutdown mode (I
temperature–to–digital conversion process is halted. The
LM75’s bus interface remains active and TEMP, T
T
or SCL due to external bus activity may increase the standby
power consumption. If the LM75 is in Interrupt Mode, the
state of INT/CMPTR will be RESET upon entering
shutdown mode.
Fault Queue
INT/CMPTR the LM75 may be programmed to filter out
transient events. This is done by programming the desired
value into the Fault Queue. Logic inside the LM75 will
prevent the device from triggering INT/CMPTR unless the
programmed number of sequential temperature–to–digital
conversions yield the same qualitative result. In other words,
the value reported in TEMP must remain above T
below T
HYST
MSB
The four most significant bits of the Address Byte (A6,
INT/CMPTR behaves differently depending on whether
When the appropriate bit is set in the configuration
To lessen the probability of spurious activation of
1
may be read from and written to. Transitions on SDA
HYST
SET
0
. When in Comparator Mode, INT/CMPTR
for the consecutive number of cycles
0
DD
= 1 A, typical) and the
1
A2
HYST
A1
, whereupon
SET
SET
LSB
A0
, and
HYST
or
,