LM95010CIMM National Semiconductor, LM95010CIMM Datasheet - Page 9

• Manufacturer Part Number: LM95010CIMM
• Description: Digital Temperature Sensor with SensorPath Bus in MSOP8 Package
• Manufacturer: National Semiconductor

1.0 Functional Description
drive by the master. Signals labels that begin with the label
Slv_ depict the drive by the LM95010. All other signals show
what would be seen when probing SWD for a particular
function (e.g. "Master Wr 0" is the Master transmitting a Data
Bit with the value of 0).
1.2.1 Bus Inactive
The bus is inactive when the SWD signal is high for a period
of at least t
signal".
1.2.2 Data Bit 0 and 1
All Data Bit signal transfers are started by the master. A Data
Bit 0 is indicated by a "short" pulse; a Data Bit 1 is indicated
by a longer pulse. The direction of the bit is relative to the
master, as follows:
A master must monitor the bus as inactive before starting a
Data Bit (read or Write).
A master initiates a data write by driving the bus active (low
level) for the period that matches the data value (t
for a write of "0" or "1", respectively). The LM95010 will
detect that the SWD becomes active within a period of
t
is active in order to detect the data value.
A master initiates a data read by driving the bus for a period
of t
active within a period of t
LM95010 will not drive the SWD. For a data read of "1" the
LM95010 will start within t
period of t
the time at which the bus becomes inactive to identify a data
read of "0" or "1".
During each Data Bit, both the master and all the LM95010s
must monitor the bus (the master for Attention Request and
Reset; at the LM95010s for Start Bit, Attention Request and
Reset) by measuring the time SWD is active (low). If a Start
Bit, Attention Requests or Reset "bit signal" is detected, the
current "bit signal" is not treated as a Data Bit.
Note that the bit rate of the protocol varies depending on the
data transferred. Thus, the LM95010 has a value of "0" in
reserved or unused register bits for bus bandwidth efficiency.
1.2.3 Start Bit
A master must monitor the bus as inactive before beginning
a Start Bit.
The master uses a Start Bit to indicate the beginning of a
transfer. LM95010s will monitor for Start Bits all the time, to
allow synchronization of transactions with the master. If a
Start Bit occurs in the middle of a transaction, the LM95010
being addressed will abort the current transaction. In this
case the transaction is not "completed" by the LM95010 (see
Section 1.3 "SensorPath Bus Transactions").
During each Start Bit, both the master and all the LM95010s
must monitor the bus for Attention Request and Reset, by
• Data Write - a Data Bit transferred from the master to the
• Data Read - a Data Bit transferred from the LM95010 to
SFEdet
Mtr0
LM95010.
the master.
, and will start measuring the duration of that the SWD
. The LM95010 will detect that the SWD have become
SLout1
INACT
. Both master and LM95010 must monitor
. The bus is inactive between each "bit
SFEdet
SFEdet
. For a data read of "0", the
to drive the SWD low for a
(Continued)
Mtr0
or t
Mtr1
9
measuring the time SWD is active (low). If an Attention
Request or Reset condition is detected, the current "bit
signal" is not treated as a Start Bit. The master may attempt
to send the Start Bit at a later time.
1.2.4 Attention Request
The LM95010 may initiate an Attention Request when the
SensorPath bus is inactive.
Note that a Data Bit, or Start Bit, from the master may start
simultaneously with an Attention Request from the
LM95010. In addition, two LM95010s may start an Attention
Request simultaneously. Due to its length, the Attention Re-
quest has priority over any other "bit signal", except Reset.
Conflict with Data Bits and Start Bits are detected by all the
devices, to allow the bits to be ignored and re-issued by their
originator.
The LM95010 will either check to see that the bus is inactive
before starting an Attention Request, or start the Attention
Request with the t
active. The LM95010 will drive the signal low for t
After this, both the master and the LM95010 must monitor
the bus for a Reset Condition. If a Reset condition is de-
tected, the current "bit signal" is not treated as an Attention
Request.
After Reset, an Attention Request can not be sent before the
master has sent 14 Data Bits on the bus. See Section 1.3.5
for further details on Attention Request generation.
1.2.5 Bus Reset
The LM95010 issues a Reset at power up. The master must
also generate a Bus Reset at power-up for at least the
minimum reset time, it must not rely on the LM95010. Sen-
sorPath puts no limitation on the maximum reset time of the
master. Following a Bus Reset, the LM95010 may generate
an Attention Request only after the master has sent 14 Data
Bits on the bus. See section 1.3.5 for further details on
Attention Request generation.
1.3 SensorPath BUS TRANSACTIONS
SensorPath is designed to work with a single master and up
to seven slave devices. Each slave has a unique address.
The LM95010’s supports up to 4 device addresses that are
selected by the state of the address pins ADD0 and ADD1.
The Register Set of the LM95010 is defined in Section 2.0.
1.3.1 Bus Reset Operation
A Bus Reset Operation is global on the bus and affects only
the communication interface of all the devices connected to
it. The Bus Reset operation does not affect either the con-
tents of the device registers, or device operation, to the
extent defined in LM95010 Register Set, see Section 2.0.
The Bus Reset operation is performed by generating a Reset
signal on the bus. The master must apply Reset after power-
up, and before it starts operation. The Reset signal end will
be monitored by all the LM95010s on the bus.
After the Reset Signal the SensorPath specification requires
that the master send a sequence of 8 Data Bits with a value
of "0", without a preceding Start Bit. This is required to
enable slaves that "train" their clocks to the bit timing. The
LM95010 does not require nor does it support clock training.
SFEdet
time interval after SWD becomes
www.national.com
SLoutA
time.