HCS109D Intersil Corporation, HCS109D Datasheet

no-image

HCS109D

Manufacturer Part Number
HCS109D
Description
Radiation Hardened Dual JK Flip Flop
Manufacturer
Intersil Corporation
Datasheet
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Cosmic Ray Upset Immunity < 2 x 10
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
• Input Current Levels Ii
Description
The Intersil HCS109MS is a Radiation Hardened Dual JK
Flip Flop with set and reset. The flip flop changes state with
the positive transition of the clock (CP1 or CP2).
The HCS109MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS109MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCS109DMSR
HCS109KMSR
HCS109D/Sample
HCS109K/Sample
HCS109HMSR
Bit-Day (Typ)
(Typ)
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
PART NUMBER
10
RAD (Si)/s 20ns Pulse
5 A at VOL, VOH
TEMPERATURE RANGE
12
o
C to +125
RAD (Si)/s
-55
-55
o
o
C to +125
C to +125
-9
+25
+25
+25
Errors/Bit-Day
o
o
o
o
C
C
C
C
2
/mg
-9
o
o
C
C
Errors/
103
Pinouts
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
GND
CP1
SCREENING LEVEL
Q1
Q1
R1
K1
S1
J1
HCS109MS
MIL-STD-1835 CDFP4-F16, LEAD FINISH C
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
FLATPACK PACKAGE (FLATPACK)
16 LEAD CERAMIC DUAL-IN-LINE
16 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
CP1
Q1
Q1
R1
K1
S1
J1
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
TOP VIEW
TOP VIEW
Radiation Hardened
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
Dual JK Flip Flop
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
Spec Number
9
File Number
PACKAGE
VCC
R2
J2
K2
CP2
S2
Q2
Q2
VCC
R2
J2
K2
CP2
S2
Q2
Q2
518748
2466.2

Related parts for HCS109D

HCS109D Summary of contents

Page 1

... The HCS109MS is supplied lead Ceramic flatpack (K suffi SBDIP Package (D suffix). Ordering Information PART NUMBER TEMPERATURE RANGE HCS109DMSR HCS109KMSR HCS109D/Sample HCS109K/Sample HCS109HMSR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HCS109MS Pinouts ...

Page 2

Functional Diagram 5 (11 (14 (13 (12 (15 VCC GND *Unpredictable and ...

Page 3

Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage ...

Page 4

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTES 1, 2) PARAMETER SYMBOL CONDITIONS TPLH VCC = 4.5V VCC = 4.5V TPHL VCC = 4.5V VCC = 4. TPLH VCC = 4.5V VCC = 4.5V ...

Page 5

TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Quiescent Current ICC VCC = 5.5V, VIN = VCC or GND Output Current (Sink) IOL VCC = 4.5V, VIN = VCC or GND, VOUT = 0.4V Output Current IOH VCC ...

Page 6

CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTES: 1. Alternate group A testing in ...

Page 7

... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

Page 8

AC Timing Diagrams VIH INPUT VS VIL TPLH VOH VS OUTPUT VOL TTLH VOH 80% 20% OUTPUT VOL AC VOLTAGE LEVELS PARAMETER HCS VCC 4.50 VIH 4.50 VS 2.25 VIL 0 GND 0 Pulse Width, Setup, Hold Timing Diagram Positive ...

Page 9

Die Characteristics DIE DIMENSIONS mils 2.25 x 2.24mm METALLIZATION: Type: AlSi Å Å Metal Thickness: 11k 1k GLASSIVATION: Type: SiO 2 Å Å Thickness: 13k 2.6k WORST CASE CURRENT DENSITY <2 A/cm BOND ...

Related keywords