HCS573D Intersil Corporation, HCS573D Datasheet

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HCS573D

Manufacturer Part Number
HCS573D
Description
Radiation Hardened Octal Transparent Latch/ Three-State
Manufacturer
Intersil Corporation
Datasheet
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
• Input Current Levels Ii
Description
The Intersil HCS573MS is a Radiation Hardened octal transpar-
ent three-state latch with an active low output enable. The
HCS573MS utilizes advanced CMOS/SOS technology. The
outputs are transparent to the inputs when the Latch Enable (LE)
is HIGH. When the Latch Enable (LE) goes LOW, the data is
latched. The Output Enable (OE) controls the tri-state outputs.
When the Output Enable (OE) is HIGH, the outputs are in the
high impedance state. The latch operation is independent of the
state of the Output Enable.
The HCS573MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS573MS is supplied in a 20 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCS573DMSR
HCS573KMSR
HCS573D/Sample
HCS573K/Sample
HCS573HMSR
Day (Typ)
- Bus Driver Outputs - 15 LSTTL Loads
- VIL = 0.3 VCC Max
- VIH = 0.7 VCC Min
PART NUMBER
10
RAD (Si)/s 20ns Pulse
5 A at VOL, VOH
TEMPERATURE RANGE
12
o
C to +125
RAD (Si)/s
-55
-55
o
o
C to +125
C to +125
+25
+25
+25
o
o
o
o
C
C
C
C
2
/mg
-9
o
o
C
C
Errors/Bit-
324
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
Octal Transparent Latch, Three-State
SCREENING LEVEL
Pinouts
GND
OE
D0
D1
D2
D3
D4
D5
D6
D7
HCS573MS
MIL-STD-1835 CDFP4-F20, LEAD FINISH C
MIL-STD-1835 CDIP2-T20, LEAD FINISH C
FLATPACK PACKAGE (FLATPACK)
20 LEAD CERAMIC DUAL-IN-LINE
20 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
OE
D0
D1
D2
D3
D4
D5
D6
D7
10
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
10
TOP VIEW
TOP VIEW
Radiation Hardened
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
Spec Number
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
PACKAGE
11
File Number
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
518771
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
4056

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HCS573D Summary of contents

Page 1

... SBDIP Package (D suffix). Ordering Information PART NUMBER TEMPERATURE RANGE HCS573DMSR HCS573KMSR HCS573D/Sample HCS573K/Sample HCS573HMSR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HCS573MS Octal Transparent Latch, Three-State ...

Page 2

Functional Diagram OUTPUT ENABLE High Level L = Low Level X = Immaterial Z = High Impedance I = Low voltage ...

Page 3

Absolute Maximum Ratings Supply Voltage (VCC -0.5V to +7.0V Input Voltage Range, All Inputs . . ...

Page 4

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Data to Qn TPLH VCC = 4.5V TPHL TPLH VCC = 4.5V TPHL VCC = 4.5V Enable to Output TPZL VCC = 4.5V TPZH VCC = 4.5V Disable to ...

Page 5

TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Quiescent Current ICC VCC = 5.5V, VIN = VCC or GND Output Current (Sink) IOL VCC = 4.5V, VIN = VCC or GND, VOUT = 0.4V Output Current IOH VCC ...

Page 6

CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTES: 1. Alternate Group A testing in ...

Page 7

... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

Page 8

AC Timing Diagrams INPUT LEVEL DATA VS VS TPLH QN VS FIGURE 1. LATCH ENABLE PROPAGATION DELAYS TTLH VOH 80% 20% OUTPUT VOL FIGURE 3. DATA SET-UP AND HOLD TIMES AC Load Circuit HCS573MS INPUT LEVEL ...

Page 9

Three-State Low Timing Diagram VIH INPUT VS VIL TPZL VOZ VT OUTPUT VOL THREE-STATE LOW VOLTAGE LEVELS PARAMETER HCS VCC 4.50 VIH 4.50 VS 2.25 VT 2.25 VW 0.90 GND 0 Three-State HighTiming Diagram VIH INPUT VS VIL TPZH VOH ...

Page 10

Die Characteristics DIE DIMENSIONS: 101 x 85 mils METALLIZATION: Type: SiAl Å Å Metal Thickness: 11k 1k GLASSIVATION: Type: SiO 2 Å Å Thickness: 13k 2.6k WORST CASE CURRENT DENSITY <2 A/cm BOND PAD SIZE: 100 ...

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