HCS240D Intersil Corporation, HCS240D Datasheet

no-image

HCS240D

Manufacturer Part Number
HCS240D
Description
Radiation Hardened Octal Buffer/Line Driver/ Three-State
Manufacturer
Intersil Corporation
Datasheet
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
• Input Current Levels Ii
Description
The Intersil HCS240MS is a Radiation Hardened Inverting
Octal Buffer/Line Driver, Three-State, with two active-low
output enables.
The HCS240MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS240MS is supplied in a 20 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCS240DMSR
HCS240KMSR
HCS240D/Sample
HCS240K/Sample
HCS240HMSR
Bit-Day (Typ)
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
PART NUMBER
10
RAD (Si)/s 20ns Pulse
5 A at VOL, VOH
TEMPERATURE RANGE
12
o
C to +125
RAD (Si)/s
-55
-55
o
o
C to +125
C to +125
+25
+25
+25
o
o
o
o
C
C
C
C
2
/mg
-9
o
o
C
C
Errors/
1
Pinouts
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
Octal Buffer/Line Driver, Three-State
GND
BO4
BO3
BO2
BO1
SCREENING LEVEL
AI1
AI2
AI3
AI4
AE
HCS240MS
MIL-STD-1835 CDFP4-F20, LEAD FINISH C
MIL-STD-1835 CDIP2-T20, LEAD FINISH C
FLATPACK PACKAGE (FLATPACK)
20 LEAD CERAMIC DUAL-IN-LINE
20 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
BO4
BO3
BO2
BO1
AI1
AI2
AI3
AI4
AE
10
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
10
TOP VIEW
TOP VIEW
Radiation Hardened
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
Spec Number
File Number
PACKAGE
VCC
BE
AO1
BI4
AO2
BI3
AO3
BI2
AO4
BI1
VCC
BE
AO1
BI4
AO2
BI3
AO3
BI2
AO4
BI1
518837
3562.1

Related parts for HCS240D

HCS240D Summary of contents

Page 1

... SBDIP Package (D suffix). Ordering Information PART NUMBER TEMPERATURE RANGE HCS240DMSR HCS240KMSR HCS240D/Sample HCS240K/Sample HCS240HMSR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HCS240MS Octal Buffer/Line Driver, Three-State ...

Page 2

Functional Diagram AO1 AI1 H = High Voltage Level, L =Low Voltage Level X = Immaterial, Z =High Impedance HCS240MS AO2 AO3 AO4 BO1 BO2 ...

Page 3

Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage ...

Page 4

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Propagation Delay TPHL1 VCC = 4.5V, VIH = 4.5V, VIL = 0V Propagation Delay TPLH1 VCC = 4.5V, VIH = 4.5V, VIL = 0V Propagation Delay TPZL1 VCC = 4.5V, VIH = ...

Page 5

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Supply Current ICC VCC = 5.5V, VIN = VCC or GND Output Current IOH VCC = VIH = 4.5V, VOUT = VCC -0.4V, (Source) VIL = 0 Output Current (Sink) IOL ...

Page 6

CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTE: 1. Alternate group A testing in ...

Page 7

Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method ...

Page 8

Propagation Delay Timing Diagram VIH INPUT VS VSS TPLH VOH VS OUTPUT VOL Transition Timing Diagram TTLH VOH 80% 20% OUTPUT VOL VOLTAGE LEVELS PARAMETER HCS VCC 4.50 VIH 4.50 VS 2.25 VIL 0 GND 0 Three-State High Timing Diagrams ...

Page 9

Three-State Low Timing Diagrams VIH INPUT VS VSS TPZL VOZ VT OUTPUT VOL THREE-STATE LOW VOLTAGE LEVELS PARAMETER HCS VCC 4.50 VIH 4.50 VS 2.25 VT 2.25 VW 0.90 GND 0 HCS240MS Three-State Low Load Circuit TPLZ VW UNITS V ...

Page 10

... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

Related keywords