ATTIny13-12PI ATMEL Corporation, ATTIny13-12PI Datasheet
ATTIny13-12PI
Related parts for ATTIny13-12PI
ATTIny13-12PI Summary of contents
Page 1
... Operating Voltage: – 1.8 - 5.5V for ATtiny13V – 2.7 - 5.5V for ATtiny13 • Speed Grade – ATtiny13V MHz @ 1.8 - 5.5V MHz @ 2.7 - 5.5V – ATtiny13 MHz @ 2.7 - 5.5V MHz @ 4.5 - 5.5V • Industrial Temperature Range • Low Power Consumption – Active Mode: 1 MHz, 1.8V: 240µA – Power-down Mode: < ...
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... Block Diagram ATtiny13 2 The ATtiny13 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny13 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ...
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... The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny13 as listed on page 49. Reset input. A low level on this pin for longer than the minimum pulse length will gener- ate a reset, even if the clock is not running ...
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... AVR CPU Core Introduction Architectural Overview ATtiny13 4 This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 3. Block Diagram of the AVR Architecture ...
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... The ALU operations are divided into three main categories – arithmetic, logical, and bit-func- tions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruc- tion Set” section for a detailed description. ATtiny13 5 ...
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... Status Register ATtiny13 6 The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code ...
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... Data Space. Although not being phys- ically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. ATtiny13 0 Addr. R0 ...
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... The X-register, Y-register, and Z-register Stack Pointer ATtiny13 8 The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 5. ...
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... The user software can write logic one to the I-bit to enable nested inter- rupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. ATtiny13 , directly generated from the selected clock CPU ...
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... ATtiny13 10 There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position( cleared ...
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... This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATtiny13 11 ...
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... The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny13 Program Counter (PC) is nine bits wide, thus addressing the 512 Program memory locations. “Memory Programming” on page 100 contains a detailed description on Flash data serial downloading using the SPI pins. ...
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... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 64 bytes of internal data SRAM in the ATtiny13 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 7. ...
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... EEDR ATtiny13 14 The ATtiny13 contains 64 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endur- ance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
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... X • Bit 7 – Res: Reserved Bit This bit is reserved for future use and will always read ATtiny13. For compatibility with future AVR devices, always write this bit to zero. After reading, mask out this bit. • Bit 6 – Res: Reserved Bit This bit is reserved in the ATtiny13 and will always read as zero. • ...
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... Atomic Byte Programming Split Byte Programming Erase Write ATtiny13 16 one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation ...
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... EEPROM_write(unsigned char ucAddress, unsigned char ucData Wait for completion of previous write */ while(EECR & (1<<EEPE Set Programming mode */ EECR = (0<<EEPM1)|(0>>EEPM0) /* Set up address and data registers */ EEARL = ucAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); } ATtiny13 17 ...
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... Preventing EEPROM Corruption ATtiny13 18 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_read ...
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... The I/O space definition of the ATtiny13 is shown in “Register Summary” on page 153. All ATtiny13 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instruc- tions ...
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... Flash Clock – clk FLASH ADC Clock – clk ADC ATtiny13 20 Figure 11 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “ ...
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... Internal RC Oscillator running at 9.6 MHz with longest start-up time and an initial system clock prescaling of 8. This default setting ensures that all users can make their desired clock source setting using an In-System or High-voltage Programmer. ATtiny13 (1) CKSEL1..0 01, 10 ...
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... Initial Value 0 • Bit 7 – Res: Reserved Bit This bit is reserved bit in the ATtiny13 and will always read as zero. • Bits 6..0 – CAL6..0: Oscillator Calibration Value Writing the calibration byte to this address will trim the internal Oscillator to remove pro- cess variations from the Oscillator frequency. This is done automatically during Chip Reset ...
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... MCU is kept in Reset during such changes in the clock frequency. Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page 24 for details. ATtiny13 Max Frequency in Percentage of Nominal Frequency 100% 150% ...
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... CLKPCE bit. • Bits 6..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits These bits define the division factor between the selected clock source and the internal system clock ...
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... Here the previous clock period, and T2 is the period corresponding to the new prescaler setting. CLKPS0 Clock Division Factor Reserved 1 0 Reserved 1 1 Reserved 0 0 Reserved 0 1 Reserved 1 0 Reserved 1 1 Reserved ATtiny13 128 256 25 ...
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... File and SRAM are unaltered when the device wakes up from sleep reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Figure 11 on page 20 presents the different clock systems in the ATtiny13, and their dis- tribution. The figure is helpful in selecting an appropriate sleep mode. ...
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... MCU. Refer to “External Inter- rupts” on page 52 for details. Table 11. Active Clock Domains and Wake-up Sources in the Different Sleep Modes Active Clock Domains Sleep Mode Idle X ADC Noise Reduction Power-down Note: 1. For INT0, only level interrupt. ATtiny13 Oscillators Wake-up Sources ( ...
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... Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins ATtiny13 28 There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possi- ble, and the sleep mode should be selected so that as few as possible of the device’s functions are operating ...
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... The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in “Clock Sources” on page 21. The ATtiny13 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ) ...
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... ATtiny13 30 Figure 13. Reset Logic Power-on Reset Circuit Brown-out BODLEVEL [1..0] Reset Circuit Pull-up Resistor SPIKE FILTER Watchdog Oscillator Generator CKSEL[1:0] SUT[1:0] (1) Table 12. Reset Characteristics Symbol Parameter Power-on Reset Threshold Voltage (rising) V POT Power-on Reset Threshold Voltage (2) (falling) RESET Pin Threshold V RST Voltage ...
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... Figure 14. MCU Start-up, RESET Tied POT RST RESET t TOUT TIME-OUT INTERNAL RESET Figure 15. MCU Start-up, RESET Extended Externally V POT V CC RESET TIME-OUT INTERNAL RESET rise. The RESET signal is activated CC decreases below the detection level RST t TOUT ATtiny13 is below the CC 31 ...
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... MCU after the Time-out period – t Figure 16. External Reset During Operation CC ATtiny13 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection ...
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... Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. ...
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... Reset Flags. ATtiny13 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. The voltage reference has a start-up time that may influence the way it should be used. ...
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... WDE. A logic one must be written to WDE regardless of the previ- ous value of the WDE bit. 2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with the WDCE bit cleared. This must be done in one operation. ATtiny13 WDP0 WDP1 WDP2 WDP3 ...
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... ATtiny13 36 The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions. (1) Assembly Code Example WDT_off: ; Turn off global interrupt cli ...
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... Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period. Bit WDIF WDIE WDP3 Read/Write R/W R/W R/W Initial Value ATtiny13 WDCE WDE WDP2 WDP1 WDP0 R/W R/W R/W R ...
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... ATtiny13 38 • Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. ...
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... Number of WDT Oscillator Typical Time-out at Cycles 2K (2048) cycles 4K (4096) cycles 8K (8192) cycles 16K (16384) cycles 32K (32768) cycles 64K (65536) cycles 128K (131072) cycles 256K (262144) cycles 512K (524288) cycles 1024K (1048576) cycles Reserved ATtiny13 0.125 s 0.25 s 0.5 s 1.0 s 2.0 s 4.0 s 8.0 s ...
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... Interrupts Interrupt Vectors in ATtiny13 ATtiny13 40 This section describes the specifics of the interrupt handling as performed in ATtiny13. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 9. Table 18. Reset and Interrupt Vectors Vector Program No. Address Source 1 0x0000 RESET 2 0x0001 ...
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... Most port pins are multiplexed with alternate functions for the peripheral fea- tures on the device. How each alternate function interferes with the port pin is described in “Alternate Port Functions” on page 46. Refer to the individual module sections for a full description of the alternate functions. ATtiny13 R pu Logic See Figure " ...
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... Ports as General Digital I/O Configuring the Pin ATtiny13 42 Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. The ports are bi-directional I/O ports with optional internal pull-ups. Figure 21 shows a functional description of one I/O-port pin, here generically called Pxn. ...
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... XXX SYNC LATCH PINxn r17 I/O Pull-up Comment Input No Tri-state (Hi-Z) Pxn will source current if ext. pulled Input Yes low. Input No Tri-state (Hi-Z) Output No Output Low (Sink) Output No Output High (Source) XXX in r17, PINx 0x00 t pd, max t pd, min ATtiny13 and t pd,max pd,min 0xFF 43 ...
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... ATtiny13 44 Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low ...
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... If a logic high level (“one”) is present on an asynchronous external interrupt pin config- ured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set ATtiny13 45 ...
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... Unconnected Pins Alternate Port Functions ATtiny13 46 when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode) ...
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... AIOxn PUD: PULLUP DISABLE WDx: WRITE DDRx RDx: READ DDRx RRx: READ PORTx REGISTER WRx: WRITE PORTx RPx: READ PORTx PIN WPx: WRITE PINx clk : I/O CLOCK I/O DIxn: DIGITAL INPUT PIN n ON PORTx AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx ATtiny13 PTOExn WPx 47 ...
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... ATtiny13 48 Table 20 summarizes the function of the overriding signals. The pin and port indexes from Figure 24 are not shown in the succeeding tables. The overriding signals are gen- erated internally in the modules having the alternate function. Table 20. Generic Description of Overriding Signals for Alternate Functions ...
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... Bits 7, 2– Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bit 6 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). ...
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... ATtiny13 50 Table 22. Overriding Signals for Alternate Functions in PB5..PB3 Signal PB5/RESET/ Name ADC0/PCINT5 (1) (1) PUOE RSTDISBL • DWEN PUOV 1 (1) (1) DDOE RSTDISBL • DWEN DDOV debugWire Transmit PVOE 0 PVOV 0 PTOE 0 (1) DIEOE RSTDISBL + (PCINT5 • PCIE + ADC0D) DIEOV ADC0D DI PCINT5 Input ...
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... R/W Initial Value Bit – – DDB5 Read/Write R R R/W Initial Value Bit – – PINB5 Read/Write R R R/W Initial Value 0 0 N/A ATtiny13 PORTB4 PORTB3 PORTB2 PORTB1 R/W R/W R/W R DDB4 DDB3 DDB2 DDB1 R/W R/W R/W R ...
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... External Interrupts MCU Control Register – MCUCR ATtiny13 52 The External Interrupts are triggered by the INT0 pin or any of the PCINT5..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT5..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. ...
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... Bits 7, 4..0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled ...
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... Bits 7, 6 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bits 5..0 – PCINT5..0: Pin Change Enable Mask 5..0 Each PCINT5..0 bit selects whether pin change interrupt is enabled on the correspond- ing I/O pin. If PCINT5..0 is set and the PCIE bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin ...
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... Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B) A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 25. For the actual placement of I/O pins, refer to “Pinout ATtiny13” on page 1. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “8-bit Timer/Counter Register Description” on page 66 ...
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... Definitions Timer/Counter Clock Sources Counter Unit ATtiny13 56 Compare pins (OC0A and OC0B). See “Output Compare Unit” on page 57. for details. The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare interrupt request. Many register and bit references in this section are written in general form. A lower case “ ...
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... Figure 27 shows a block diagram of the Output Compare unit. Figure 27. Output Compare Unit, Block Diagram OCRnx top bottom Waveform Generator FOCn ). clk can be generated from an external or internal T0 is present or not. A CPU write overrides (has T0 DATA BUS TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) WGMn1:0 COMnX1:0 ATtiny13 OCnx 57 ...
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... Compare Match Blocking by TCNT0 Write Using the Output Compare Unit ATtiny13 58 The OCR0x Registers are double buffered when using any of the Pulse Width Modula- tion (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence ...
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... Table 27 on page 66, and for phase correct PWM refer to Table 28 on page 67. A change of the COM0x1:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0x strobe bits. ATtiny13 OCnx ...
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... Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode ATtiny13 60 The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM02:0) and Compare Output mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do ...
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... PWM mode is shown in Figure 30. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0. f clk_I/O = ------------------------------------------------- - OCRnx ATtiny13 61 ...
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... ATtiny13 62 Figure 30. Fast PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the com- pare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins ...
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... The PWM waveform is generated by clearing (or setting) the OC0x Register at the Compare Match between OCR0x and TCNT0 when the counter incre- ments, and setting (or clearing) the OC0x Register at Compare Match between OCR0x ATtiny13 OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set ...
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... Timer/Counter Timing Diagrams ATtiny13 64 and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f OCnx PCPWM The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode ...
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... PWM mode where OCR0A is TOP. Figure 35. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC) OCRnx OCFnx ATtiny13 /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP BOTTOM + 1 /8) clk_I/O OCRnx + 2 BOTTOM + 1 65 ...
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... Timer/Counter Register Description Timer/Counter Control Register A – TCCR0A ATtiny13 66 Bit COM0A1 COM0A0 COM0B1 Read/Write R/W R/W R/W Initial Value • Bits 7:6 – COM01A:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to ...
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... Set OC0B on Compare Match, clear OC0B at TOP Note special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 61 for more details. ATtiny13 (1) (1) 67 ...
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... PWM Mode” on page 63 for more details. • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 32 ...
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... The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the “Timer/Counter Control Register A – TCCR0A” on page 66. ...
Page 70
... Bits 7..4, 0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled ...
Page 71
... Bits 7..4, 0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bit 3 – OCF0B: Output Compare Flag 0 B The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector ...
Page 72
... Timer/Counter Prescaler Prescaler Reset External Clock Source ATtiny13 72 The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (f the prescaler can be used as a clock source. The prescaled clock has a frequency of ...
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... PSR10 bit is cleared by hardware, and the Timer/Counter start counting. • Bit 0 – PSR10: Prescaler Reset Timer/Counter0 When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. ATtiny13 clk T0 T0) is shown in Figure 36 ...
Page 74
... ADC Control and Status Register B – ADCSRB Analog Comparator Control and Status Register – ACSR ATtiny13 74 The Analog Comparator compares the input values on the positive pin AIN0 and nega- tive pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set ...
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... Comparator interrupt is activated. When written logic zero, the interrupt is disabled. • Bit 2 – Res: Reserved Bit This bit is a reserved bit in the ATtiny13 and will always read as zero. • Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator inter- rupt ...
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... Analog Comparator Multiplexed Input Digital Input Disable Register 0 – DIDR0 ATtiny13 possible to select any of the ADC3..0 pins to replace the negative input to the Ana- log Comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX1 ...
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... Interrupt on ADC Conversion Complete • Sleep Mode Noise Canceler The ATtiny13 features a 10-bit successive approximation ADC. The ADC is connected to a 4-channel Analog Multiplexer which allows four single-ended voltage inputs con- structed from the pins of Port B. The single-ended voltage inputs refer to 0V (GND). ...
Page 78
... Operation ATtiny13 78 Figure 39. Analog to Digital Converter Block Schematic 8-BIT DATA BUS ADC MULTIPLEXER SELECT (ADMUX) MUX DECODER V CC INTERNAL 1.1V REFERENCE ADC3 ADC2 INPUT MUX ADC1 ADC0 The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage internal 1 ...
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... Interrupt Flag, ADIF is cleared or not. If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conver- sion was started. ATtiny13 PRESCALER START ADATE CONVERSION ...
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... Prescaling and Conversion Timing ATtiny13 80 Figure 41. ADC Prescaler ADEN START CK ADPS0 ADPS1 ADPS2 By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate ...
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... Conversion Complete One Conversion Conversion Complete ATtiny13 Next Conversion Sign and MSB of Result LSB of Result MUX and REFS Update Next Conversion Sign and MSB of Result LSB of Result MUX and REFS Update Next Conversion ...
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... ATtiny13 82 Figure 45. ADC Timing Diagram, Free Running Conversion One Conversion 11 Cycle Number ADC Clock ADSC ADIF ADCH ADCL Conversion Complete Table 36. ADC Conversion Time Condition First conversion Normal conversions Auto Triggered conversions Next Conversion Sign and MSB of Result LSB of Result Sample & ...
Page 83
... However, the simplest method is to wait for the first conversion to complete, and then change the channel selection. Since the next conversion has already started automati- cally, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. ATtiny13 83 ...
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... ADC Voltage Reference ADC Noise Canceler ATtiny13 84 The reference voltage for the ADC (V Single ended channels that exceed V selected as either internal 1.1V reference, or external AREF pin. The first ADC CC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. ...
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... Signal components higher than the Nyquist frequency (f avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. Figure 46. Analog Input Circuitry I IH ADCn I IL ATtiny13 /2) should not be present to ADC 1..100 S ...
Page 86
... Analog Noise Canceling Techniques ADC Accuracy Definitions ATtiny13 86 Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks ...
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... Figure 49. Integral Non-linearity (INL) Output Code • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. ATtiny13 Gain Error Ideal ADC Actual ADC V Input Voltage ...
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... REFS0 ADLAR Read/Write R R/W R/W Initial Value • Bit 7 – Res: Reserved Bit This bit is reserved bit in the ATtiny13 and will always read as zero. • Bit 6 – REFS0: Reference Selection Bit V Input Voltage REF 1024 -------------------------- V REF the selected voltage refer- ...
Page 89
... ADC Data Register – ADCL and ADCH” on page 90. • Bits 4:2 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bits 1:0 – MUX1:0: Analog Channel Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC ...
Page 90
... The ADC Data Register – ADCL and ADCH ADLAR = 0 ADLAR = 1 ATtiny13 90 When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB. ...
Page 91
... Bits 7, 5..3 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bits 2:0 – ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect ...
Page 92
... ATtiny13 92 When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC3..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the dig- ital input buffer ...
Page 93
... When designing a system where debugWIRE will be used, the following observations must be made for correct operation: • Pull-Up resistor on the dW/(RESET) line must be in the range of 10k However, the pull-up resistor is optional. • Connecting the RESET pin directly to V 1.8 - 5.5V VCC dW(RESET) GND will not work. CC ATtiny13 93 ...
Page 94
... Software Break Points Limitations of debugWIRE debugWIRE Related Register in I/O Memory debugWire Data Register – DWDR ATtiny13 94 • Capacitors inserted on the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. debugWIRE supports Program memory Break Points by the AVR Break instruction. Set- ting a Break Point in AVR Studio memory ...
Page 95
... SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. • The CPU is halted during the Page Write operation. ATtiny13 95 ...
Page 96
... Addressing the Flash During Self- Programming ATtiny13 96 The Z-pointer is used to address the SPM commands. Bit (R31) Z15 Z14 Z13 ZL (R30 Since the Flash is organized in pages (see Table 46 on page 102), the Program Counter can be treated as having two different sections. One section, consisting of the least sig- nificant bits, is addressing the words within a page, while the most significant bits are addressing the pages ...
Page 97
... Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and always read as zero. • Bit 4 – CTPB: Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost. ...
Page 98
... EEPROM Write Prevents Writing to SPMCSR Reading the Fuse and Lock Bits from Software ATtiny13 98 Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation recommended that the user checks the status bit (EEWE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register ...
Page 99
... The calibrated RC Oscillator is used to time Flash accesses. Table 41 shows the typical programming time for Flash accesses from the CPU. Table 41. SPM Programming Time Symbol Flash write (Page Erase, Page Write, and write Lock bits by SPM) ATtiny13 Min Programming Time Max Programming Time 3 This CC 4 ...
Page 100
... This section describes the different methods for Programming the ATtiny13 memories. The ATtiny13 provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional security listed in Table 43. The Lock bits can only be erased to “1” with the Chip Erase command. ...
Page 101
... Fuse Bytes 2535B–AVR–01/04 The ATtiny13 has two Fuse bytes. Table 44 and Table 45 describe briefly the functional- ity of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. ...
Page 102
... KB Flash memory). 3. 0x002: 0x07 (indicates ATtiny13 device when 0x001 is 0x90). Signature area of the ATtiny13 has one byte of calibration data for the internal RC Oscil- lator. This byte resides in the high byte of address 0x000. During reset, this byte is automatically written into the OSCCAL Register to ensure correct frequency of the cali- brated RC Oscillator ...
Page 103
... Low:> 2 CPU clock cycles for f < 12 MHz, 3 CPU clock cycles for f ck High:> 2 CPU clock cycles for f < 12 MHz, 3 CPU clock cycles for f ck ATtiny13 (1) +1.8 - 5.5V VCC PB2 SCK PB1 ...
Page 104
... When writing serial data to the ATtiny13, data is clocked on the rising edge of SCK. When reading data from the ATtiny13, data is clocked on the falling edge of SCK. See Figure 54 and Figure 55 for timing details. To program and verify the ATtiny13 in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in Table 50): 1 ...
Page 105
... Table 49. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol t WD_FLASH t WD_EEPROM t WD_ERASE t WD_FUSE Figure 54. Serial Programming Waveforms SERIAL DATA INPUT MSB (MOSI) SERIAL DATA OUTPUT MSB (MISO) SERIAL CLOCK INPUT (SCK) SAMPLE value. Minimum Wait Delay 4.5 ms 4.0 ms 4.0 ms 4.5 ms ATtiny13 WD_EEPROM LSB LSB 105 ...
Page 106
... Read Calibration Byte 0011 1000 Poll RDY/BSY 1111 0000 Note address high bits address low bits Low byte High Byte data out data in don’t care ATtiny13 106 Instruction Format Byte 2 Byte 3 Byte4 0101 0011 xxxx xxxx ...
Page 107
... SHOX t SCK Low to MISO Valid SLIV Note for f < 12 MHz CLCL ck This section describes how to program and verify Flash Program memory, EEPROM Data memory, Lock bits and Fuse bits in the ATtiny13 SLSH SHOX t SHSL t SLIV = - ...
Page 108
... ATtiny13 108 Figure 56. High-voltage Serial Programming +11.5 - 12.5V SERIAL CLOCK INPUT Table 52. Pin Name Mapping Signal Name in High-voltage Serial Programming Mode Pin Name SDI PB0 SII PB1 SDO PB2 SCI PB3 The minimum period for the Serial Clock Input (SCI) during High-voltage Serial Pro- gramming is 220 ns ...
Page 109
... Programming Mode Considerations for Efficient Programming Chip Erase 2535B–AVR–01/04 To program and verify the ATtiny13 in the High-voltage Serial Programming mode, the following sequence is recommended (See instruction formats in Table 55): The following algorithm puts the device in High-voltage Serial Programming mode: 1. Apply 4.5 - 5.5V between Set RESET pin to “ ...
Page 110
... Repeat 2 through 3 until the entire Flash is programmed or until all data has been programmed. 5. End Page Programming by Loading Command “No Operation”. When writing or reading serial data to the ATtiny13, data is clocked on the rising edge of the serial clock, see Figure 58, Figure 59 and Table 56 for details. Figure 57. Addressing the Flash which is Organized in Pages ...
Page 111
... The algorithms for programming and reading the Fuse Low/High bits and Lock bits are shown in Table 55. The algorithms for reading the Signature bytes and Calibration byte are shown in Table 55. Set SCI to “0”. Set RESET to “1”. Turn V ATtiny13 power off. CC 111 ...
Page 112
... Table 55. High-voltage Serial Programming Instruction Set for ATtiny13 Instruction Instr.1/5 SDI 0_1000_0000_00 Chip Erase SII 0_0100_1100_00 SDO x_xxxx_xxxx_xx SDI 0_0001_0000_00 Load “Write Flash” SII 0_0100_1100_00 Command SDO x_xxxx_xxxx_xx SDI 0_ bbbb_bbbb _00 SII 0_0000_1100_00 SDO x_xxxx_xxxx_xx Load Flash Page Buffer SDI ...
Page 113
... Table 55. High-voltage Serial Programming Instruction Set for ATtiny13 (Continued) Instruction Instr.1/5 SDI 0_0000_0011_00 Load “Read EEPROM” SII 0_0100_1100_00 Command SDO x_xxxx_xxxx_xx SDI 0_bbbb_bbbb_00 Read EEPROM SII 0_0000_1100_00 Byte SDO x_xxxx_xxxx_xx SDI 0_0100_0100_00 Write Fuse Low SII 0_0100_1100_00 Bits SDO x_xxxx_xxxx_xx ...
Page 114
... High-voltage Serial Programming Characteristics ATtiny13 114 Figure 59. High-voltage Serial Programming Timing SDI (PB0), SII (PB1) SCI (PB3) SDO (PB2) Table 56. High-voltage Serial Programming Characteristics V otherwise noted) Symbol Parameter t SCI (PB3) Pulse Width High SHSL t SCI (PB3) Pulse Width Low SLSH t SDI (PB0), SII (PB1) Valid to SCI (PB3) High ...
Page 115
... WDT enabled WDT disabled ATtiny13 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied ...
Page 116
... CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL t Change in period from one clock cycle to the next CLCL Maximum Speed vs ATtiny13 116 IH1 V = 1.8 - 5.5V CC Min. 0 1000 400 400 Maximum frequency is depending on V Maximum Frequency vs. V curve is linear between 1.8V < ...
Page 117
... To calculate required voltage for a maximum frequency, use this equation:: Voltage At 19 MHz this gives: Voltage Thus, a maximum frequency of 19 MHz requires V Figure 61. Maximum Frequency vs MHz 6 MHz 1.8V Figure 62. Maximum Frequency vs MHz 12 MHz 2.7V 0.9 0. 0.9 0.15 19 3.75V = + = = 3. ATtiny13V CC Safe Operating Area 2.7V , ATtiny13 CC Safe Operating Area 4.5V 5.5V ATtiny13 5.5V 117 ...
Page 118
... Offset Error Conversion Time Clock Frequency V Input Voltage IN Input Bandwidth V Internal Voltage Reference INT R Analog Input Resistance AIN Notes: 1. Values are preliminary. ATtiny13 118 (1) Condition Min Single Ended Conversion Single Ended Conversion 4V, REF CC ADC clock = 200 kHz Single Ended Conversion V ...
Page 119
... ATtiny13 Typical Characteristics – Preliminary Data Active Supply Current 2535B–AVR–01/04 The following charts show typical behavior. These figures are not tested during manu- facturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail- to-rail output is used as clock source ...
Page 120
... ATtiny13 120 Figure 64. Active Supply Current vs. Frequency ( MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1. Figure 65. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 9 1 4.0V 3.3V 2. ...
Page 121
... Figure 67. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V INTERNAL WD OSCILLATOR, 128 KHz 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 1.5 2 2.5 (Internal RC Oscillator, 4.8 MHz 3 (V) CC (Internal WDT Oscillator, 128 kHz 3 (V) CC ATtiny13 25 °C -40 °C 85 °C 5.5 -40 °C 25 °C 85 °C 5.5 121 ...
Page 122
... Idle Supply Current ATtiny13 122 Figure 68. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V 0.04 0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 1.5 2 2.5 Figure 69. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 0.1 0.2 0.3 (32 kHz External Clock kHz EXTERNAL CLOCK 3 3 ...
Page 123
... IDLE SUPPLY CURRENT vs. FREQUENCY Figure 71. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 9.6 MH 2.5 2 1.5 1 0.5 0 1 4.0V 3.3V 2.7V 1. Frequency (MHz) (Internal RC Oscillator, 9.6 MHz 3.5 4 4.5 V (V) CC ATtiny13 5.5V 5.0V 4. °C 25 °C -40 °C 5 5.5 123 ...
Page 124
... ATtiny13 124 Figure 72. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 4.8 MH 1.2 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 Figure 73. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V INTERNAL WD OSCILLATOR, 128 KH 0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 1.5 2 2.5 (Internal RC Oscillator, 4.8 MHz 3 (V) CC (Internal RC Oscillator, 128 kHz) ...
Page 125
... Figure 75. Power-Down Supply Current vs. V POWER-DOWN SUPPLY CURRENT vs. V 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 (32 kHz External Clock 32kHz EXTERNAL CLOCK 3 3.5 4 4.5 V (V) CC (Watchdog Timer Disabled WATCHDOG TIMER DISABLED 3 3.5 4 4.5 V (V) CC ATtiny13 85 °C 25 °C -40 °C 5 5.5 85 ˚C -40 ˚C 25 ˚C 5 5.5 125 ...
Page 126
... Pin Pull-up ATtiny13 126 Figure 76. Power-Down Supply Current vs. V POWER-DOWN SUPPLY CURRENT vs 1.5 2 2.5 Figure 77. I/O Pin Pull-up Resistor Current vs. Input Voltage (V I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 160 140 25 ˚C 85 ˚C 120 -40 ˚C 100 ...
Page 127
... Figure 79. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 120 25 ˚C -40 ˚C 100 85 ˚ 2.7V 2.7 CC 1.5 2 2 (V) RESET ATtiny13 3 = 5V) 5 127 ...
Page 128
... Pin Driver Strength ATtiny13 128 Figure 80. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 60 25 ˚C -40 ˚ ˚ 0.5 1 Figure 81. I/O Pin Source Current vs. Output Voltage (Low Power Ports, V I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE ...
Page 129
... Figure 83. I/O Pin Source Current vs. Output Voltage (Low Power Ports, V I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE 7 -40 ˚C 25 ˚ ˚ 0.2 0.4 0.6 = 2.7V CC 1.5 2 2.5 V (V) OH LOW POWER PORTS 1.8V CC 0.8 1 1.2 1.4 1.6 V (V) OH ATtiny13 = 2.7V 1.8V) CC 1.8 2 129 ...
Page 130
... ATtiny13 130 Figure 84. I/O Pin Sink Current vs. Output Voltage (Low Power Ports, V I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE LOW POWER PORTS 0.5 Figure 85. I/O Pin Sink Current vs. Output Voltage (Low Power Ports, V I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE ...
Page 131
... Figure 87. I/O Pin Source Current vs. Output Voltage (V I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE 90 80 -40 ˚ ˚ ˚ LOW POWER PORTS, 1.8V 0.8 1 1.2 1.4 1.6 1 (V) OH ATtiny13 = 1.8V) CC -40 ˚C 25 ˚C 85 ˚ 131 ...
Page 132
... ATtiny13 132 Figure 88. I/O Pin Source Current vs. Output Voltage (V I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE 35 30 -40 ˚C 25 ˚ ˚ 0.5 1 Figure 89. I/O Pin Source Current vs. Output Voltage (V I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE 10 -40 ˚ ˚ ˚ ...
Page 133
... I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 100 0.5 Figure 91. I/O Pin Sink Current vs. Output Voltage (V I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0 -40 ˚C 25 ˚C 85 ˚ 2.7V 2.7V CC -40 ˚C 25 ˚C 85 ˚ (V) OL ATtiny13 2.5 2.5 133 ...
Page 134
... ATtiny13 134 Figure 92. I/O Pin Sink Current vs. Output Voltage (V I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.2 0.4 0.6 Figure 93. Reset Pin as I/O - Source Current vs. Output Voltage (V RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE 1.6 1.4 -40 ˚C 1.2 25 ˚ ˚C 0.8 0.6 0.4 0 1.8V 1.8V CC 0.8 1 1.2 1.4 1.6 1 ...
Page 135
... Figure 94. Reset Pin as I/O - Source Current vs. Output Voltage (V RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE 2.5 -40 ˚ ˚C 85 ˚C 1 0.5 1 Figure 95. Reset Pin as I/O - Source Current vs. Output Voltage (V RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE 2.5 -40 ° °C 1.5 85 ° 0.2 0.4 0 2.7V CC 1.5 2 2 1.8V CC 0.8 1 1.2 1.4 1.6 1.8 V (V) OH ATtiny13 = 2.7V 1.8V) 2 135 ...
Page 136
... ATtiny13 136 Figure 96. Reset Pin as I/O - Sink Current vs. Output Voltage (V RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE 0.5 Figure 97. Reset Pin as I/O - Sink Current vs. Output Voltage (V RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE 4.5 4 3.5 3 2.5 2 1 0 -40 ˚C 25 ˚C 85 ˚ ...
Page 137
... RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE 1.6 1.4 1.2 1 0.8 0.6 0.4 0 0.2 0.4 0.6 Figure 99. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs 2.5 2 1.5 1 0.5 0 1.5 2 2.5 = 1.8V 1.8V CC 0.8 1 1.2 1.4 1.6 V (V) OL (VIH, I/O Pin Read as '1 VIH, IO PIN READ AS '1' 3 3 (V) CC ATtiny13 -40 ˚C 25 ˚C 85 ˚C 1 ˚C 25 ˚C -40 ˚C 5.5 137 ...
Page 138
... ATtiny13 138 Figure 100. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs 2.5 2 1.5 1 0.5 0 1.5 2 2.5 Figure 101. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V 0.45 0.4 -40 ºC 0.35 0.3 25 ºC 0.25 0.2 85 ºC 0.15 0.1 0.05 0 1.5 2 2.5 (VIL, I/O Pin Read as '0 VIL, IO PIN READ AS '0' 3 3 (V) ...
Page 139
... Figure 103. Reset Pin as I/O - Input Threshold Voltage vs. V '0') RESET PIN AS I/O - THRESHOLD VOLTAGE vs. V 2.5 2 1.5 85 ˚ ˚C 0.5 -40 ˚C 0 1.5 2 2.5 (VIH, Reset Pin Read CC CC VIH, IO PIN READ AS '1' 3 3 (V) CC (VIL, Reset Pin Read VIL, IO PIN READ AS '0' 3 3 (V) CC ATtiny13 5.5 5.5 139 ...
Page 140
... ATtiny13 140 Figure 104. Reset Pin as I/O - Pin Hysteresis vs. V RESET PIN PIN HYSTERESIS vs. V 0.7 0.6 -40 ºC 0.5 25 ºC 0.4 85 ºC 0.3 0.2 0.1 0 1.5 2 2.5 Figure 105. Reset Input Threshold Voltage vs. V RESET INPUT THRESHOLD VOLTAGE vs. V 2.5 2 1.5 -40 ˚ ˚C 25 ˚C 0.5 0 1 3 (V) CC ...
Page 141
... Figure 107. Reset Input Pin Hysteresis vs. V RESET INPUT THRESHOLD VOLTAGE vs. V 0.5 -40 ºC 0.4 0.3 85 ºC 0.2 25 ºC 0.1 0 1.5 2 2.5 (VIL, Reset Pin Read as '0 VIL, IO PIN READ AS '0' 3 3 VIL, IO PIN READ AS '0' 3 3.5 4 4.5 V (V) CC ATtiny13 5.5 5 5.5 141 ...
Page 142
... BOD Thresholds and Analog Comparator Offset ATtiny13 142 Figure 108. BOD Thresholds vs. Temperature (BODLEVEL is 4.3V) BOD THRESHOLDS vs. TEMPERATURE 4.5 4.4 4.3 4.2 -60 -40 -20 Figure 109. BOD Thresholds vs. Temperature (BODLEVEL is 2.7V) BOD THRESHOLDS vs. TEMPERATURE 2.9 2.8 2.7 2.6 -60 -40 -20 V BODLEVEL IS 4.3 Rising V CC Falling Temperature (C) V BODLEVEL IS 2.7 Rising V CC ...
Page 143
... Figure 110. BOD Thresholds vs. Temperature (BODLEVEL is 1.8V) BOD THRESHOLDS vs. TEMPERATURE 1.9 1.85 1.8 1.75 -60 -40 -20 Figure 111. Bandgap Voltage vs. V BANDGAP VOLTAGE vs. V 1.06 1.04 1.02 1 0.98 0.96 0.94 0.92 1.5 2.5 V BODLEVEL IS 1.8 Rising V CC Falling Temperature ( 3.5 4.5 V (V) CC ATtiny13 100 85ºC 25ºC -40ºC 5.5 143 ...
Page 144
... ATtiny13 144 Figure 112. Analog Comparator Offset Voltage vs. Common Mode Voltage (V ANALOG COMPARATOR OFFSET vs. COMMON MODE VOLTAGE 0.008 0.007 0.006 0.005 0.004 0.003 0.002 0.001 0 0 0.5 1 1.5 Figure 113. Analog Comparator Offset Voltage vs. Common Mode Voltage (V ANALOG COMPARATOR OFFSET vs. COMMON MODE VOLTAGE ...
Page 145
... Figure 114. Calibrated 9.6 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 9.6 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 10.3 10.1 9.9 9.7 9.5 5.5 V 9.3 4.5 V 9.1 2.7 V 8.9 1.8 V 8.7 8.5 -60 -40 -20 Figure 115. Calibrated 9.6 MHz RC Oscillator Frequency vs. V CALIBRATED 9.6 MHz RC OSCILLATOR FREQUENCY vs 10.5 10 9.5 9 8.5 8 1 Temperature ( 3 (V) CC ATtiny13 100 CC 85 ˚C 25 ˚C -40 ˚C 5.5 145 ...
Page 146
... ATtiny13 146 Figure 116. Calibrated 9.6 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 9.6MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE Figure 117. Calibrated 4.8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 4.8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 5.1 5 4.9 4.8 1.8 V 4.7 5.5 V 4.0 V 4.6 2.7 V 4.5 -60 -40 - ...
Page 147
... Figure 119. Calibrated 4.8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 4.8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 3 104 112 OSCCAL VALUE ATtiny13 CC 85 ˚C 25 ˚C -40 ˚C 5.5 25 ˚C 120 127 147 ...
Page 148
... ATtiny13 148 Figure 120. 128 kHz Watchdog Oscillator Frequency vs. V 128 kHz WATCHDOG OSCILLATOR FREQUENCY vs. V 120 115 110 105 100 1.5 2 2.5 Figure 121. 128 kHz Watchdog Oscillator Frequency vs. Temperature 128 kHz WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 118 116 114 112 110 108 ...
Page 149
... Figure 122. Brownout Detector Current vs. V BROWNOUT DETECTOR CURRENT vs 1.5 2 2.5 Figure 123. ADC Current vs 350 300 250 200 150 100 50 0 1 3.5 4 4.5 V (V) CC ADC CURRENT vs 3.5 4 4.5 V (V) CC ATtiny13 -40 ˚C 25 ˚C 85 ˚C 5 5.5 -40 ˚C 25 ˚C 85 ˚C 5 5.5 149 ...
Page 150
... ATtiny13 150 Figure 124. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT vs. V 140 120 100 1.5 2 2.5 Figure 125. Programming Current vs. V PROGRAMMING CURRENT vs. Vcc 4 3.5 3 2.5 2 1.5 -40 ° °C 0.5 85 °C 0 1 3 3 (V) CC -40 ˚C 25 ˚ ...
Page 151
... RESET SUPPLY CURRENT vs MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP 3.5 3 2.5 2 1 (0.1 - 1.0 MHz, Excluding Current through CC CC 0.4 0.5 0.6 0.7 0.8 Frequency (MHz MHz, Excluding Current through the CC CC 4.0V 3.3V 2.7V 1. Frequency (MHz) ATtiny13 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0.9 1 5.5V 5.0V 4. 151 ...
Page 152
... ATtiny13 152 Figure 128. Reset Pulse Width vs. V RESET PULSE WIDTH vs. V 2500 2000 1500 1000 500 0 1.8 2.1 2.5 2 3.3 3.5 4 4.5 5 5 ºC 25 ºC -40 ºC 6 2535B–AVR–01/04 ...
Page 153
... REFS0 ADLAR – – ADSC ADATE ADIF ADIE ADC Data Register High Byte ADC Data Register Low Byte ACME – – – – – – ATtiny13 Bit 2 Bit 1 Bit – – – – – – – – – OCIE0A TOIE0 – ...
Page 154
... Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. ATtiny13 154 2535B–AVR–01/04 ...
Page 155
... then then then then then then then then then then then PC I/O(P,b) I/O(P,b) Rd(n+1) Rd(n) Rd(n+1), Rd(7) Rd(0) C,Rd(n+1) ATtiny13 Operation Flags Z,C,N,V,H Z,C,N,V,H Rdh:Rdl + K Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Rdh:Rdl - K Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Rr Z,N,V Rd ...
Page 156
... Store Program Memory IN Rd Port OUT P, Rr Out Port PUSH Rr Push Register on Stack POP Rd Pop Register from Stack MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break ATtiny13 156 Description Rd(7) C,Rd(n) Rd(n) Rd(n+1), n=0..6 Rd(3..0) Rd(7..4),Rd(7..4) Rd(3..0) SREG(s) SREG(s) T Rr(b) Rd( ...
Page 157
... Wide, Plastic Dual Inline Package (PDIP) 8S2 8-lead, 0.209" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC) S8S1 8-lead, 0.150" Wide, Plastic Gull-Wing Small Outline (JEDEC SOIC) 2535B–AVR–01/04 (1) Ordering Code Package ATtiny13-12PI 8P3 (2) ATtiny13-12PJ 8P3 ATtiny13-12SI 8S2 (2) ATtiny13-12SJ ...
Page 158
... E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 2325 Orchard Parkway San Jose, CA 95131 R ATtiny13 158 ...
Page 159
... TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ End View COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A 1.70 A1 0.05 b 0.35 C 0.15 D 5.13 E1 5.18 E 7.70 L 0.51 0˚ e 1.27 BSC DRAWING NO. ATtiny13 NOTE 2.16 0.25 0.48 5 0.35 5 5.35 5. 8.26 0.85 8˚ 4 10/7/03 REV. 8S2 C 159 ...
Page 160
... S8S1 Top View e L Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums,etc. 2325 Orchard Parkway San Jose, CA 95131 R ATtiny13 160 Side View End View TITLE S8S1, 8-lead, 0.150" Wide Body, Plastic Gull Wing Small ...
Page 161
... Errata ATtiny13 Rev. C ATtiny13 Rev. B 2535B–AVR–01/04 The revision letter in this section refers to the revision of the ATtiny13 device. There are no known errata for this revision. • Wrong values read after Erase Only operation • High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may fail • ...
Page 162
... ATtiny13 Rev. A ATtiny13 162 Problem fix/ Workaround Do not ship products with on-chip debug of the tiny13 enabled. 5. Watchdog Timer Interrupt disabled If the watchdog timer interrupt flag is not cleared before a new timeout occurs, the watchdog will be disabled, and the interrupt flag will automatically be cleared. This is only applicable in interrupt only mode ...
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... Characteristics” on page 115. 8. Added “Maximum Speed vs. VCC” on page 116 9. Updated “ADC Characteristics – Preliminary Data” on page 118. 10. Updated “ATtiny13 Typical Characteristics – Preliminary Data” on page 119. 11. Updated “Ordering Information” on page 157. 12. Updated “Packaging Information” on page 158. ...
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... ATtiny13 164 2535B–AVR–01/04 ...
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... ALU – Arithmetic Logic Unit.................................................................................. 5 Status Register ..................................................................................................... 6 General Purpose Register File ............................................................................. 7 Stack Pointer ........................................................................................................ 8 Instruction Execution Timing................................................................................. 9 Reset and Interrupt Handling................................................................................ 9 AVR ATtiny13 Memories ................................................................... 12 In-System Re-programmable Flash Program Memory ....................................... 12 SRAM Data Memory........................................................................................... 13 EEPROM Data Memory...................................................................................... 14 I/O Memory ......................................................................................................... 19 System Clock and Clock Options .................................................... 20 Clock Systems and their Distribution .................................................................. 20 Clock Sources ...
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... ATtiny13 ii Interrupts ............................................................................................ 40 Interrupt Vectors in ATtiny13 .............................................................................. 40 I/O Ports.............................................................................................. 41 Introduction ......................................................................................................... 41 Ports as General Digital I/O ................................................................................ 42 Alternate Port Functions ..................................................................................... 46 Register Description for I/O-Ports....................................................................... 51 External Interrupts ............................................................................. 52 8-bit Timer/Counter0 with PWM........................................................ 55 Overview............................................................................................................. 55 Timer/Counter Clock Sources............................................................................. 56 Counter Unit........................................................................................................ 56 Output Compare Unit.......................................................................................... 57 Compare Match Output Unit ............................................................................... 59 Modes of Operation ............................................................................................ 60 Timer/Counter Timing Diagrams......................................................................... 64 8-bit Timer/Counter Register Description ...
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... External Clock Drive Waveforms ...................................................................... 116 External Clock Drive ......................................................................................... 116 Maximum Speed vs. V .................................................................................. 116 CC ADC Characteristics – Preliminary Data........................................................... 118 ATtiny13 Typical Characteristics – Preliminary Data ................... 119 Active Supply Current ....................................................................................... 119 Idle Supply Current ........................................................................................... 122 Power-Down Supply Current ............................................................................ 125 Pin Pull-up ........................................................................................................ 126 Pin Driver Strength ........................................................................................... 128 Pin Thresholds and Hysteresis ...
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... ATtiny13 iv Datasheet Change Log for ATtiny13 .............................................. 163 Changes from Rev. 2535A-06/03 to Rev. 2535B-01/04 ................................... 163 Table of Contents ................................................................................. i 2535B–AVR–01/04 ...
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... Fax: (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...