P80C562 Philips Semiconductors, P80C562 Datasheet - Page 24

• Manufacturer Part Number: P80C562
• Description: 8-bit microcontroller
• Manufacturer: Philips Semiconductors

Philips Semiconductors
13 SERIAL I/O
The P8xC562 is equipped with a full duplex UART port and
is identical to the serial port of the 80C51 (see ‘Single-chip
8-bit Microcontrollers User Manual’ .
14 INTERRUPT SYSTEM
External events and the real-time driven on-chip
peripherals require service by the CPU asynchronously to
the execution of any particular section of code. To tie the
asynchronous activities of these functions to normal
program execution a multiple-source, two-priority-level,
nested interrupt system is provided. The interrupt system
is shown in Fig.12. Interrupt response latency is from
2.25 s to 6 s when using a 16 MHz crystal.
The P8xC562 acknowledges interrupt requests from
14 sources as follows:
Each interrupt vectors to a separate location in program
memory for its service routine. Each source can be
individually enabled or disabled by a corresponding bit in
the IEN0 or IEN1 registers, in addition each interrupt may
be programmed to a high or low priority level using the
corresponding bit in the IP0 or IP1 registers. All enabled
sources can be globally disabled or enabled. Both external
interrupts can be programmed to be level-activated or
transition-activated; an active LOW level allows
'wire-ORing' of several interrupt sources to the input pin.
1997 Apr 08
INT0 and INT1: externally via pins P3.2/INT0 and
P3.3/INT1 respectively
Timer 0 and Timer 1: from the two internal counters
Timer T2 (8 separate interrupts): 4 capture interrupts,
3 compare interrupts and an overflow interrupt. If the
Capture Register remains unused and its contents are
'don't care', then the corresponding input pin CTnI may
be used as a positive and/or negative edge triggered
external interrupt.
ADC conversion completed interrupt
UART serial I/O port interrupt.
8-bit microcontroller
24
14.1
Table 24 gives the vector address in Program Memory
where the appropriate interrupt service routine is located.
Table 24 Interrupt vectors
14.2
Each interrupt source can be either high priority or low
priority. If both priorities are requested simultaneously, the
processor will branch to the high priority vector. If there are
simultaneous requests from sources of the same priority,
then interrupts will be serviced in the following order:
X0, ADC, T0, CT0, CM0, X1, CT1, CM1, T1, CT2, CM2,
S0, CT3, T2.
A low priority interrupt routine can only be interrupted by a
high priority interrupt. A high priority interrupt routine can
not be interrupted.
External 0
Timer 0 overflow
External 1
Timer 1 overflow
Serial I/O 0 (UART)
T2 capture 0
T2 capture 1
T2 capture 2
T2 capture 3
ADC completion
T2 compare 0
T2 compare 1
T2 compare 2
T2 overflow
Interrupt Vectors
Interrupt priority
SOURCE
P83C562; P80C562
X0
T0
X1
T1
S0
CT0
CT1
CT2
CT3
ADC
CM0
CM1
CM2
T2
SYMBOL
Product specification
VECTOR
000BH
001BH
003BH
004BH
005BH
006BH
0003H
0013H
0023H
0033H
0043H
0053H
0063H
0073H