M306V0ME Mitsubishi, M306V0ME Datasheet - Page 34

• Manufacturer Part Number: M306V0ME
• Description: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
• Manufacturer: Mitsubishi

34
Table 2.4.9 Software waits and bus cycles
Note: When using the RDY signal, always set to “0.”
• OSD RAM
ROM/RAM
External
memory
Internal
Area
SFR
area
(9) Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
0005
A software wait is inserted in the internal ROM/RAM area, in the OSD RAM area (Note 2), and in the
external memory area by setting the wait bit of the processor mode register 1. When set to “0”, each
bus cycle is executed in one BCLK cycle. When set to “1”, each bus cycle is executed in two or three
BCLK cycles. After the microcomputer has been reset, this bit defaults to “0”. When set to “1”, a wait is
applied to all memory areas (two or three BCLK cycles), regardless of the contents of bits 4 to 7 of the
chip select control register. Set this bit after referring to the recommended operating conditions (main
clock input oscillation frequency) of the electric characteristics. However, when the user is using the
RDY signal, the relevant bit in the chip select control register’s bits 4 to 7 must be set to “0.”
When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for
each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register
correspond to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed
in one BCLK cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits
default to “0” after the microcomputer has been reset. These bits default to “0” after the microcomputer
has been reset.
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits.
Also, the corresponding bits of the chip select control register must be set to “0” if using the multiplex
bus to access the external memory area.
Table 2.4.9 shows the software wait and bus cycles. Figure 2.4.8 shows example bus timing when
using software waits.
Notes 1: Before attempting to change the contents of the processor mode register 1, set bit 1 of the
________
16
) (Note 1) and bits 4 to 7 of the chip select control register (address 0008
2: Be sure to set a software wait to access to OSD RAM.
Multiplex bus
Multiplex bus
Separate bus
Separate bus
Separate bus
Bus status
protect register (address 000A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Wait bit
Invalid
_______
0
1
0
0
1
0
1
_______
Bits 4 to 7 of chip select
control register
16
) to “1”.
0 (Note)
0 (Note)
Invalid
Invalid
Invalid
0
1
0
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
2 BCLK cycles
3 BCLK cycles
3 BCLK cycles
and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
Bus cycle
M306V0ME-XXXFP
16
M306V0EEFP
).
Rev. 1.0