X40010 Xicor, X40010 Datasheet - Page 12

• Manufacturer Part Number: X40010
• Description: Dual Voltage Monitor with Integrated CPU Supervisor
• Manufacturer: Xicor

X40010/X40011/X40014/X40015 – Preliminary
SERIAL DEVICE ADDRESSING
Memory Address Map
CR, Control Register, CR7: CR0
Address: 1FF
FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FF
Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
– a device type identifier that is always ‘101x’. Where
– next two bits are ‘0’.
– next bit that becomes the MSB of the address.
REV 1.3.4 7/12/02
Figure 12. Current Address Read Sequence
.
Figure 13. Random Address Read Sequence
x=0 is for Array, x=1 is for Control Register or Fault
Detection Register.
hex
hex
Signals from
Signals from
the Master
the Slave
SDA Bus
S
a
r
t
t
Signals from
Signals from
1 0 1
the Master
the Slave
SDA Bus
Address
Slave
0
0
0
S
a
A
C
K
t
r
t
1 0 1 0
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Address
Address
Byte
Slave
0
0
Figure 11. X40010/11/14/15 Addressing
Control Register
Fault Detection Register
Control Register
Fault Detection Register
1
A
C
K
S
a
r
t
t
Address
Slave
Data
Characteristics subject to change without notice.
1
C
A
K
Slave Byte
Word Address
1
1
1
1
S
o
p
t
Data
0
0
1
1
1
1
1
1
1
1
1
1
S
o
p
0
0
t
1
1
0
0
1
1
1
0
1
1
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R/W
R/W
1
1