X4003 Xicor, X4003 Datasheet
X4003
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X4003 Summary of contents
Page 1
... Reset & Watchdog Timebase Power on and Low Voltage + Reset Generation - V TRIP www.xicor.com detection circuitry protects the CC falls below the minimum V CC returns to CC thresholds are available; however, Xicor’s RESET (X4003) RESET (X4005) Characteristics subject to change without notice. trip ...
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... X4003/X4005 PIN CONFIGURATION 8-Pin JEDEC SOIC, MSOP RESET PIN DESCRIPTION Pin Pin Pin (SOIC/DIP) TSSOP (MSOP REV 1.1.3 4/30/ SCL SDA Name NC No internal connections NC No internal connections ...
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... X4003/X4005 PRINCIPLES OF OPERATION Power On Reset Application of power to the X4003/X4005 activates a power on reset circuit that pulls the RESET/RESET pin active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. – It prevents the processor from operating prior to stabilization of the oscillator. – ...
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... LOW to complete the operation. is 4.4V TRIP must TRIP > 3V 15-18V 15-18V 03h X4003/ www.xicor.com is reset, the new V TRIP TRIP voltage, apply the desired TRIP pin and tie the Then write 00h to P programming sequence. Bring WP ...
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... See "Writing to the Control Register" below. The user must issue a stop after sending the control byte to the register to initiate the nonvolatile cycle that stores WD1 and WD0. The X4003/X4005 will not acknowledge any data bytes written after the first byte is entered. www.xicor.com ...
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... The state of the control register can be read at any time by performing a serial read operation. Only one byte is read by each register read operation. The X4003/X4005 resets itself after the first byte is read. The master should supply a stop condition to be con- sistent with the bus protocol, but a stop is not required to end this operation ...
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... The device will respond with an acknowledge after rec- ognition of a start condition and the correct contents of the slave address byte. Acknowledge bits are also pro- vided by the X4003/4005 after correct reception of the control register address byte, after receiving the byte written to the control register and after the second slave address in a read question (See Figure 8 and See Figure 9 ...
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... X4003/X4005 Figure 7. Acknowledge Response From Receiver SCL from Master Data Output from Transmitter Data Output from Receiver Start SERIAL WRITE OPERATIONS Slave Address Byte Following a start condition, the master must output a slave address byte. This byte consists of several parts: – a device type identifier that is always ‘1011’. ...
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... X4003/X4005 Serial Read Operations The read operation allows the master to access the control 2 register. To conform to the I C standard, prior to issuing the slave address byte with the R/W bit set to one, the master must first perform a “dummy” write operation. The master issues the start condition and the slave address byte, receives an acknowledge, then issues the byte address ...
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... X4003/X4005 ABSOLUTE MAXIMUM RATINGS Temperature under bias ................... -65°C to +135°C Storage temperature ........................ -65°C to +150°C Voltage on any pin with respect to V .......................................-1.0V to +7V SS D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds).........300°C RECOMMENDED OPERATING CONDITIONS Temperature Min. Commercial 0°C Industrial -40°C D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) ...
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... X4003/X4005 CAPACITANCE (T = 25° 1.0 MHz Symbol (4) C Output capacitance (SDA, RESET/RESET) OUT (4) C Input capacitance (SCL, WP) IN Note: (4) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUIT 5V For V = 0.4V OL 1533Ω and SDA 100pF A.C. CHARACTERISTICS (Continued)(Over recommended operating conditions, unless otherwise specified) ...
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... X4003/X4005 TIMING DIAGRAMS Bus Timing t F SCL t SU:STA t HD:STA SDA IN SDA OUT WP Pin Timing Start SCL SDA IN WP Write Cycle Timing SCL th SDA 8 Bit of Last Byte Nonvolatile Write Cycle Timing Symbol (7) t Write cycle time WC Note: ( the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. ...
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... Reset trip point voltage, X4003–4.5A, X4005–4.5A TRIP Reset trip point voltage, X4003, X4005 Reset trip point voltage, X4003–2.7A, X4005–2.7A Reset trip point voltage, X4003–2.7, X4005–2.7 Reset trip point voltage, X4003–1.8, X4005–1.8 t Power-up reset time out ...
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... X4003/X4005 RESET/RESET Output Timing Symbol Parameter t Watchdog time out period, WDO WD1 = 1, WD0 = 1 (factory setting) WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = pulse width to reset the watchdog CST t Reset time out RST V Programming Timing Diagram TRIP t THD t VPO Programming Parameters ...
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... X4003/X4005 PACKAGING INFORMATION 8-Lead Plastic Small Outline Gull Wing Package Type S Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0° - 8° 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.1.3 4/30/02 Pin 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.050 (1.27) X 45° 0.0075 (0.19) 0.010 (0.25) FOOTPRINT www ...
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... X4003/X4005 PACKAGING INFORMATION 8-Lead Miniature Small Outline Gull Wing Package Type M 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.036 (0.91) 0.032 (0.81) 0.040 ± 0.002 (1.02 ± 0.05) 0.007 (0.18) 0.005 (0.13) REV 1.1.3 4/30/02 0.118 ± 0.002 (3.00 ± 0.05) 0.0256 (0.65) Typ. 0.118 ± 0.002 (3.00 ± 0.05) 0.030 (0.76) 0.0216 (0.55) 7° Typ. 0.008 (0.20) 0.004 (0.10) 0.150 (3.81) Ref. ...
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... X4003S8I–2.7 -40–85°C X4003M8I–2.7 0–70°C X4003S8–1.8 0–70°C X4003M8–1.8 8-Lead SOIC X4003/ –4. +70° –4.5A (-171740 to +85°C) Blank = No Suffix (0 to +70° Suffix (-40 to +85° –2. +70° –2.7A (-40 to +85° –2 +70° – ...
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... X4003/X4005 LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. ...