SP310E Sipex, SP310E Datasheet - Page 6

• Manufacturer Part Number: SP310E
• Description: High-Performance RS-232 Line Drivers/Receivers
• Manufacturer: Sipex

Figure 4. Charge Pump — Phase 1
In actual system applications, it is quite possible
for signals to be applied to the receiver inputs
before power is applied to the receiver circuitry.
This occurs, for example, when a PC user attempts
to print, only to realize the printer wasn’t turned on.
In this case an RS-232 signal from the PC will
appear on the receiver input at the printer. When
the printer power is turned on, the receiver will
operate normally. All of these enhanced devices
are fully protected.
Charge Pump
The charge pump is a Sipex–patented design
(5,306,954) and uses a unique approach com-
pared to older less–efficient designs. The charge
pump still requires four external capacitors, but
uses a four–phase voltage shifting technique to
attain symmetrical power supplies. There is a
free–running oscillator that controls the four
phases of the voltage shifting. A description of
each phase follows.
Phase 1
— V
the clock cycle, the positive side of capacitors
C
then switched to ground and the charge in C
transferred to C
+5V, the voltage potential across capacitor C
now 10V.
Date: 7/19/04
Figure 5. Charge Pump — Phase 2
1
and C
SS
charge storage —During this phase of
2
are initially charged to +5V. C
2
–
. Since C
C
2
1
+
+
–
C
V
is connected to
1
CC
–5V
+
–
SP202E Series High Performance RS232 Transceivers
V
= +5V
CC
= +5V
C
l
2
1
+
–
2
–10V
+
–
C
is
is
is
2
+5V
–5V
+
–
6
Phase 2
— V
nects the negative terminal of C
storage capacitor and the positive terminal of C
to ground, and transfers the generated –l0V to
C
tor C
is connected to ground.
Phase 3
— V
clock is identical to the first phase — the charge
transferred in C
terminal of C
side of capacitor C
voltage potential across C
Phase 4
— V
connects the negative terminal of C
and transfers the generated l0V across C
the V
with this, the positive side of capacitor C
switched to +5V and the negative side is con-
nected to ground, and the cycle begins again.
Since both V
from V
3
. Simultaneously, the positive side of capaci-
+
–
C
C
DD
DD
4
SS
DD
1
+
3
–
+
–
C
C
is switched to +5V and the negative side
CC
4
transfer — Phase two of the clock con-
transfer — The fourth phase of the clock
charge storage — The third phase of the
storage capacitor. Again, simultaneously
3
V
V
+
–
; in a no–load condition V
DD
SS
V
V
Storage Capacitor
Storage Capacitor
DD
SS
1
+
, which is applied to the negative
Storage Capacitor
Storage Capacitor
and V
1
produces –5V in the negative
2
. Since C
–
are separately generated
© Copyright 2004 Sipex Corporation
2
is l0V.
2
+
is at +5V, the
2
+
2
and V
to the V
to ground,
2
to C
–
will
1
SS
is
4
2
,