BS62LV2007 Brilliance Semiconductor, BS62LV2007 Datasheet

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BS62LV2007

Manufacturer Part Number
BS62LV2007
Description
Very Low Power/Voltage CMOS SRAM 256K X 8 bit
Manufacturer
Brilliance Semiconductor
Datasheet
BS62LV2007HC
R0201-BS62LV2007
BS62LV2007HI
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
• High speed access time :
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2, CE1, and OE options
PRODUCT
PIN CONFIGURATIONS
Brilliance Semiconductor Inc
FEATURES
FAMILY
Vcc = 3.0V
Vcc = 5.0V
PRODUCT FAMILY
-70
-10
BSI
100ns(Max.) at Vcc = 3.0V
70ns(Max.) at Vcc = 3.0V
0.1uA (Typ.) CMOS standby current
0.6uA (Typ.) CMOS standby current
C-grade : 20mA (Max.) operating current
C-grade : 35mA (Max.) operating current
I- grade : 25mA (Max.) operating current
I- grade : 40mA (Max.) operating current
-40
TEMPERATURE
0
OPERATING
O
O
C to +70
C to +85
Very Low Power/Voltage CMOS SRAM
256K X 8 bit
O
O
C
C
. reserves the right to modify document contents without notice.
2.4V ~5.5V
RANGE
Vcc
SPEED
70/100
70/100
(ns)
Vcc=
3.0V
The BS62LV2007 is a high performance, very low power CMOS
Static Random Access Memory organized as 262,144 words by 8 bits
and operates in a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.1uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV2007 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV2007 is available in the JEDEC standard 36 pin
Mini BGA 6x8 mm.
1
BLOCK DIAGRAM
DESCRIPTION
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE1
CE2
A15
A16
A14
A12
Vdd
Gnd
A13
A17
WE
OE
OE
A7
A6
A5
A4
25 uA
6 uA
Vcc=
5.0V
Address
Buffer
STANDBY
Input
(I
CCSB1
8
Control
8
POWER DISSIPATION
, Max)
20
0.7 uA
1.5 uA
Vcc=
3.0V
Output
Buffer
Buffer
Data
Input
Data
Decoder
Row
35 mA
40 mA
Vcc=
BS62LV2007
5.0V
8
1024
Operating
8
(I
CC
A11
, Max)
A9
Address Input Buffer
20 mA
25 mA
Column Decoder
Memory Array
A8 A3 A2 A1
Vcc=
3.0V
Sense Amp
Write Driver
Column I/O
1024 x 2048
2048
256
16
Revision 2.0
April 2002
A0
BGA-36-
TYPE
A10
0608
PKG

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BS62LV2007 Summary of contents

Page 1

... HIGH chip enable (CE2), and active LOW output enable (OE) and three-state output drivers. The BS62LV2007 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV2007 is available in the JEDEC standard 36 pin Mini BGA 6x8 mm. SPEED Vcc ...

Page 2

... UNITS -0 Vcc+0.5 Commercial O -40 to +125 C O -60 to +150 C 1.0 W CAPACITANCE 20 mA SYMBOL This parameter is guaranteed and not tested. 2 BS62LV2007 Function I/O OPERATION Vcc CURRENT High Z High Z D OUT D IN AMBIENT RANGE TEMPERATURE + Industrial - +85 ...

Page 3

... IN See Retention Waveform ( CE1 Controlled ) Data Retention Mode ≥ V 1.5V DR Vcc t CDR ≥ CE1 Vcc - 0. CE2 Controlled ) Data Retention Mode V 1.5V DR Vcc t CDR CE2 0. BS62LV2007 (1) MIN. TYP. MAX. Vcc=3.0V -0.5 -- Vcc=5.0V 2.0 Vcc=3.0V -- Vcc+0.2 2.2 Vcc=5. IL Vcc=3. Vcc=5.0V Vcc=3.0V 2.4 -- Vcc=5. Vcc=3 ...

Page 4

... Output Disable to Output Address Change 4 BS62LV2007 KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM MAY CHANGE FROM DON T CAR E: ANY CHANG E PERMITTED DOES NOT APPLY o C, Vcc = 3.0V ) BS62LV2007-70 BS62LV2007-10 MIN. TYP. MAX. MIN. TYP. MAX 100 -- -- ...

Page 5

... The parameter is guaranteed but not 100% tested. R0201-BS62LV2007 R0201-BS62LV2007 ACS1 t ACS2 (5) t CLZ OLZ t ACS1 (5) t CLZ1 t ACS2 (5) t CLZ2 and CE2 IH. = 5pF as shown in Figure 1B BS62LV2007 CHZ1 CHZ2 t OH (5) t OHZ (1,5) t CHZ1 (2,5) t CHZ2 Revision 2.0 April 2002 ...

Page 6

... Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active (5) ( (4,10) t OHZ 6 BS62LV2007 o C, Vcc = 3.0V ) BS62LV2007-70 BS62LV2007-10 MIN. TYP. MAX. MIN. TYP. MAX 100 -- 100 -- 100 -- ...

Page 7

... CE1 going low or CE2 going high to the end of write. CW R0201-BS62LV2007 (5) ( (4,10) t WHZ ). IL ± 500mV from steady state with BS62LV2007 (11) (11 WR2 ( (8, 5pF as shown in Figure 1B. The (8) Revision 2.0 April 2002 ...

Page 8

... DETAIL A 0.75 1.125 3.75 BOTTOM VIEW ( BALL SIDE ) 36 mini-BGA ( BS62LV2007 SPEED 70: 70ns 10: 100ns GRADE + - + PACKAGE Pin Mini BGA (6mm x 8mm) SOLDER BALL DETAIL A NOTE: 1. PIN#1 DOT MARKING IS BY LASER OR PAD PRINT. ...

Page 9

... BSI REVISION HISTORY Revision Description 1.0 Data Sheet release 2.0 Modify some AC parameters. Modify 5V ICCSB1_Max(I-grade) from 10uA to 25uA. R0201-BS62LV2007 Date Note Jan. 10, 2002 April,12,2002 9 BS62LV2007 Revision 2.0 April 2002 ...

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