AM29F002B Advanced Micro Devices, AM29F002B Datasheet
AM29F002B
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AM29F002B Summary of contents
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... Am29F002B/Am29F002NB Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu ...
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... Am29F002B/Am29F002NB 2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS Single power supply operation — 5.0 Volt-only operation for read, erase, and program operations — Minimizes system level requirements Manufactured on 0.32 µm process technology — Compatible with 0.5 µm Am29F002 device High performance — ...
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... GENERAL DESCRIPTION The Am29F002B Family consists of 2 Mbit, 5.0 volt-only Flash memory devices organized as 262,144 bytes. The Am29F002B offers the RESET# function, the Am29F002NB does not. The data appears on DQ7–DQ0. The device is offered in 32-pin PLCC, 32-pin TSOP, and 32-pin PDIP packages. This device is designed to be programmed in-system with the stan- dard system 5 ...
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... Figure 12. Chip/Sector Erase Operation Timings . . . . . . . . . . . . . 29 Figure 13. Data# Polling Timings (During Embedded Algorithms Figure 14. Toggle Bit Timings (During Embedded Algorithms Figure 15. DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 16. Temporary Sector Unprotect Timing Diagram (Am29F002B only Figure 17. Alternate CE# Controlled Write Operation Timings . . . 33 Erase and Programming Performance . . . . . . . 34 Latchup Characteristics . . . . . . . . . . . . . . . . . . . 34 TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 34 PLCC and PDIP Pin Capacitance ...
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... A0–A17 4 Am29F002B/Am29F002NB -55 - Sector Switches Erase Voltage Generator PGM Voltage Generator Chip Enable Output Enable Logic Y-Decoder STB Timer X-Decoder Am29F002B/Am29F002NB -90 -120 90 120 90 120 35 50 – DQ0 DQ7 Input/Output Buffers Data STB Latch Y-Gating Cell Matrix November 28, 2000 ...
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... DQ0 Standard TSOP Am29F002B/Am29F002NB NC on Am29F002NB A14 29 A13 PLCC A11 25 OE# 24 A10 23 CE# 22 DQ7 ...
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... Hardware reset pin, active low (not available on Am29F002NB +5.0 V single power supply CC (see Product Selector Guide for device speed ratings and voltage supply tolerances Device ground Pin not connected internally 6 LOGIC SYMBOL 18 A0–A17 CE# OE# WE# RESET# N/C on Am29F002NB Am29F002B/Am29F002NB 8 DQ0–DQ7 November 28, 2000 ...
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... Volt-only Program and Erase Valid Combinations AM29F002BT-55 PC, AM29F002BB-55 JC, JI, AM29F002NBT-55 EC, EI AM29F002NBB-55 AM29F002BT-70 PC, PI, AM29F002BB-70 JC, JI, AM29F002NBT-70 EC, EI AM29F002NBB-70 AM29F002BT-90 AM29F002BB-90 AM29F002NBT-90 PC, PI, PE, AM29F002NBB-90 JC, JI, JE, AM29F002BT-120 EC, EI, EE AM29F002BB-120 AM29F002NBT-120 AM29F002NBB-120 November 28, 2000 TEMPERATURE RANGE C = Commercial ( + Industrial (– +85 C) ...
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... The command register itself does not occupy any addressable memory location. The register is composed of latches that store the com- mands, along with the address and data information needed to execute the command. The contents of the Table 1. Am29F002B/Am29F002NB Device Bus Operations Operation Read Write CMOS Standby ...
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... RESET# pin is driven low. Refer to the next section, “RESET#: Hardware Reset Pin”. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. In the DC Characteristics tables, I standby current specification. Table 2. Am29F002B/Am29F002NB Top Boot Block Sector Address Table Sector A17 A16 SA0 0 0 ...
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... Table 3. Am29F002B/Am29F002NB Bottom Boot Block Sector Address Table Sector A17 A16 SA0 0 0 SA1 0 0 SA2 0 0 SA3 0 0 SA4 0 1 SA5 1 0 SA6 1 1 Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This ...
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... ID control pins. Details on this method are provided in the (Am29F002B) and 21183 (Am29F002NB). Contact an AMD representative to obtain a copy of the appropriate document. The device is shipped with all sectors unprotected. ...
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... When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using Am29F002B/Am29F002NB on address bit A9. ID November 28, 2000 ...
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... Any commands written to the device during the Embedded Program Algorithm are ignored. On the Am29F002B only, note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity ...
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... Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. On the Am29F002B only, note that a hard- ware reset dur ing the sector er ase op eratio n immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity ...
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... The system must write the Erase Resume command (address bits are “don’t care”) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. Am29F002B/Am29F002NB 15 ...
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... Command Definitions Table 5. Am29F002B/Am29F002NB Command Definitions Command Sequence (Note 1) Read (Note 5) 1 Reset (Note 6) 1 Manufacturer ID 4 Device ID, 4 Top Boot Block Auto- select Device ID, 4 (Note 7) Bottom Boot Block Sector Protect Verify 4 (Note 8) Program 4 Chip Erase 6 Sector Erase 6 Erase Suspend (Note 9) ...
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... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 4. Data# Polling Algorithm Am29F002B/Am29F002NB Yes No Yes Yes No ...
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... DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or erase cycle was not successfully completed. Am29F002B/Am29F002NB November 28, 2000 ...
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... Complete, Write Reset Command Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. See text. Figure 5. Toggle Bit Algorithm Am29F002B/Am29F002NB (Note 1) No Yes Yes (Notes Yes ...
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... DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “DQ5: Exceeded Timing Limits” for more information. 20 Table 6. Write Operation Status DQ7 (Note 1) DQ6 DQ7# Toggle 0 Toggle 1 No toggle Data Data DQ7# Toggle Am29F002B/Am29F002NB DQ5 DQ2 (Note 2) DQ3 (Note 1) 0 N/A No toggle 0 1 Toggle 0 N/A Toggle Data Data ...
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... Operating ranges define those limits between which the func- tionality of the device is guaranteed. November 28, 2000 +0.8 V –0.5 V –2.0 V Figure 6. Maximum Negative Overshoot Waveform +0.5 V 2.0 V Figure 7. Maximum Positive Overshoot Waveform Am29F002B/Am29F002NB ...
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... max CE#, OE RESET 5 mA min I = –2.5 mA min = CCmax . IH Am29F002B/Am29F002NB Min Typ Max Unit 1.0 µA 50 µA 1.0 µ 0 0 –0 0.5 11.5 12 ...
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... V CC RESET min I = –2 min I = –100 µ min = CCmax . IH Am29F002B/Am29F002NB Min Typ Max Unit 1.0 µA 50 µA 1.0 µ µ µA –0 11.5 12.5 V ...
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... Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Am29F002B/Am29F002NB All -55 others Unit 1 TTL gate L 30 100 0.0– ...
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... Max OE OE Max IL Max Max Max Read Toggle and Data# Polling t RC Addresses Stable t ACC OEH t CE HIGH Z Output Valid Figure 9. Read Operations Timings Am29F002B/Am29F002NB Speed Options -55 -70 -90 -120 Min 120 120 120 ...
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... Note: Not 100% tested. RESET# is not available on Am29F002NB. CE#, OE# RESET# n/a Am29F002NB RESET# n/a Am29F002NB 26 Test Setup Max Max Min Min Ready Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms t RP Figure 10. RESET# Timings Am29F002B/Am29F002NB All Speed Options Unit 20 µs 500 ns 500 November 28, 2000 ...
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... Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. November 28, 2000 Min Min Min Min Min Min Min Min Min Min Min Typ Typ Min Am29F002B/Am29F002NB Speed Options -55 -70 -90 -120 Unit 120 ...
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... VCS Notes program address program data WPH A0h is the true data at the program address. OUT Figure 11. Program Operation Timings Am29F002B/Am29F002NB Read Status Data (last two cycles WHWH1 Status D OUT November 28, 2000 ...
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... SA = sector address (for Sector Erase Valid Address for reading status data (”see “Write Operation Status”). Figure 12. Chip/Sector Erase Operation Timings November 28, 2000 555h for chip erase WPH t DH 55h 30h 10 for Chip Erase Am29F002B/Am29F002NB Read Status Data WHWH2 In Complete Progress 29 ...
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... Figure 14. Toggle Bit Timings (During Embedded Algorithms Complement Complement Status Data Status Data Valid Status Valid Status (first read) (second read) Am29F002B/Am29F002NB VA High Z True Valid Data High Z True Valid Data VA VA Valid Status Valid Data (stops toggling) November 28, 2000 ...
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... RSP Unprotect Note: Not 100% tested RESET VIDR CE# WE# RY/BY# Figure 16. Temporary Sector Unprotect Timing Diagram (Am29F002B only) November 28, 2000 Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Figure 15. DQ2 vs. DQ6 Min Min Program or Erase Command Sequence ...
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... WHWH2 WHWH2 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. 32 Min Min Min Min Min Min Min Min Min Min Min Typ Typ Am29F002B/Am29F002NB Speed Options -55 -70 -90 -120 Unit 120 ...
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... November 28, 2000 PA for program SA for sector erase 555 for chip erase Data# Polling GHEL t t WHWH1 CPH for program PD for program 55 for erase 30 for sector erase 10 for chip erase Am29F002B/Am29F002NB PA DQ7# D OUT = data written to device. OUT 33 ...
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... V (4.75 V for ±5% devices), 1,000,000 cycles. CC –1.0 V –1.0 V –100 mA = 5.0 V, one pin at a time. RESET# not available on Am29F002NB. CC Test Setup OUT V IN Am29F002B/Am29F002NB Unit Comments s Excludes 00h programming prior to erasure (Note 4) s µs Excludes system level overhead (Note 1,000,000 cycles. Additionally, CC Min Max 12 ...
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... Sampled, not 100% tested. 2. Test conditions 1.0 MHz. A DATA RETENTION Parameter Minimum Pattern Data Retention Time November 28, 2000 Test Conditions OUT Test Conditions 150 C 125 C Am29F002B/Am29F002NB Typ Max Unit Min Unit 10 Years 20 Years 35 ...
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... PHYSICAL DIMENSIONS PD 032—32-Pin Plastic DIP 36 Am29F002B/Am29F002NB Dwg rev AD; 10/99 November 28, 2000 ...
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... PHYSICAL DIMENSIONS (continued) PL 032—32-Pin Plastic Leaded Chip Carrier November 28, 2000 Am29F002B/Am29F002NB Dwg rev AH; 10/99 37 ...
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... PHYSICAL DIMENSIONS (continued) TS 032—32-Pin Standard Thin Small Package 38 Am29F002B/Am29F002NB Dwg rev AA; 10/99 November 28, 2000 ...
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... Replaced figures with more detailed illustrations. Revision D (November 28, 2000) Global Added table of contents. Ordering Information Deleted burn-in option. Table 5, Command Definitions In Note 4, changed the lower address bit of don’t care range to A11. Am29F002B/Am29F002NB : Added Note 2 “Maximum I CC4 ”. CC CCmax : Added Note 2 “Maximum I ...