AM79C90 Advanced Micro Devices, AM79C90 Datasheet - Page 7
![no-image](/images/manufacturer_photos/0/0/14/advanced_micro_devices_sml.jpg)
AM79C90
Manufacturer Part Number
AM79C90
Description
CMOS Local Area Network Controller for Ethernet (C-LANCE)
Manufacturer
Advanced Micro Devices
Datasheet
1.AM79C90.pdf
(62 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AM79C900AJC
Manufacturer:
AMD
Quantity:
5 510
Company:
Part Number:
AM79C900AJC
Manufacturer:
SIG
Quantity:
5 510
Company:
Part Number:
AM79C900JAJC
Manufacturer:
AMD
Quantity:
359
Company:
Part Number:
AM79C900JCDV
Manufacturer:
AMD
Quantity:
1 831
Part Number:
AM79C901AJC
Manufacturer:
AMD
Quantity:
20 000
Part Number:
AM79C901AVC
Manufacturer:
AMD
Quantity:
20 000
Part Number:
AM79C90JC
Manufacturer:
AMD
Quantity:
20 000
Low — Data is taken off the DAL lines by the
READ
(Input/Output, Three-State)
Indicates the type of operation to be performed in the
current bus cycle. This signal is an output when the
C-LANCE is a Bus Master.
High — Data is taken off the DAL lines by the
Low — Data is placed on the DAL lines by the
The signal is an input when the C-LANCE is a Bus
Slave.
High — Data is placed on the DAL lines by the
READY
(Input/Output, Open Drain)
When the C-LANCE is a Bus Master, READY is an
asynchronous acknowledgment from the bus memory
that it will accept data in a WRITE cycle or that it has
put data on the DAL lines in a READ cycle.
As a Bus Slave, the C-LANCE asserts READY when it
has put data on the DAL lines during a READ cycle or
is about to take data off the DAL lines during a write
cycle. READY is a response to DAS and will return High
after DAS has gone High. READY is an input when the
C-LANCE is a Bus Master and an output when the
C-LANCE is a Bus Slave.
RENA
Receive Enable (Input)
A logical input that indicates the presence of carrier on
the channel.
C-LANCE.
C-LANCE.
C-LANCE.
C-LANCE.
P R E L I M I N A R Y
Am79C90
RESET
Reset (Input)
Reset causes the C-LANCE to cease operation, clear
its internal logic, force all three-state buffers to the high-
impedance state, and enter an idle state with the stop
bit of CSR0 set. It is recommended that a 3.3 k pullup
resistor be connected to this pin.
RX
Receive (Input)
Receive Input Bit Stream.
TCLK
Transmit Clock (Input)
10 MHz clock.
TENA
Transmit Enable (Output)
Transmit Output Bit Stream enable. When asserted, it
enables valid transmit output (TX).
TX
Transmit (Output)
Transmit Output Bit Stream.
V
Power Supply Pin +5 V 5%
It is recommended that 0.1 F and 10 F decoupling
capacitors be used between V
V
Ground
Pin 1 and 24 (48-Pin DlPs) should be connected
together externally, as close to the chip as possible.
DD
SS
DD
and V
SS
.
7